virt/kvm/arm/vgic/vgic-v3.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  13  */
  14
  15 #include <linux/irqchip/arm-gic-v3.h>
  16 #include <linux/kvm.h>
  17 #include <linux/kvm_host.h>
  18 #include <kvm/arm_vgic.h>
  19 #include <asm/kvm_mmu.h>
  20 #include <asm/kvm_asm.h>
  21
  22 #include "vgic.h"
  23
  24 void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
  25 {
  26         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
  27         u32 model = vcpu->kvm->arch.vgic.vgic_model;
  28
  29         if (cpuif->vgic_misr & ICH_MISR_EOI) {
  30                 unsigned long eisr_bmap = cpuif->vgic_eisr;
  31                 int lr;
  32
  33                 for_each_set_bit(lr, &eisr_bmap, kvm_vgic_global_state.nr_lr) {
  34                         u32 intid;
  35                         u64 val = cpuif->vgic_lr[lr];
  36
  37                         if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
  38                                 intid = val & ICH_LR_VIRTUAL_ID_MASK;
  39                         else
  40                                 intid = val & GICH_LR_VIRTUALID;
  41
  42                         WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE);
  43
  44                         kvm_notify_acked_irq(vcpu->kvm, 0,
  45                                              intid - VGIC_NR_PRIVATE_IRQS);
  46                 }
  47
  48                 /*
  49                  * In the next iterations of the vcpu loop, if we sync
  50                  * the vgic state after flushing it, but before
  51                  * entering the guest (this happens for pending
  52                  * signals and vmid rollovers), then make sure we
  53                  * don't pick up any old maintenance interrupts here.
  54                  */
  55                 cpuif->vgic_eisr = 0;
  56         }
  57
  58         cpuif->vgic_hcr &= ~ICH_HCR_UIE;
  59 }
  60
  61 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
  62 {
  63         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
  64
  65         cpuif->vgic_hcr |= ICH_HCR_UIE;
  66 }
  67
  68 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
  69 {
  70         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
  71         u32 model = vcpu->kvm->arch.vgic.vgic_model;
  72         int lr;
  73
  74         for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
  75                 u64 val = cpuif->vgic_lr[lr];
  76                 u32 intid;
  77                 struct vgic_irq *irq;
  78
  79                 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
  80                         intid = val & ICH_LR_VIRTUAL_ID_MASK;
  81                 else
  82                         intid = val & GICH_LR_VIRTUALID;
  83                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  84
  85                 spin_lock(&irq->irq_lock);
  86
  87                 /* Always preserve the active bit */
  88                 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
  89
  90                 /* Edge is the only case where we preserve the pending bit */
  91                 if (irq->config == VGIC_CONFIG_EDGE &&
  92                     (val & ICH_LR_PENDING_BIT)) {
  93                         irq->pending = true;
  94
  95                         if (vgic_irq_is_sgi(intid) &&
  96                             model == KVM_DEV_TYPE_ARM_VGIC_V2) {
  97                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
  98
  99                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
 100                                 irq->source |= (1 << cpuid);
 101                         }
 102                 }
 103
 104                 /* Clear soft pending state when level irqs have been acked */
 105                 if (irq->config == VGIC_CONFIG_LEVEL &&
 106                     !(val & ICH_LR_PENDING_BIT)) {
 107                         irq->soft_pending = false;
 108                         irq->pending = irq->line_level;
 109                 }
 110
 111                 spin_unlock(&irq->irq_lock);
 112         }
 113 }
 114
 115 /* Requires the irq to be locked already */
 116 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 117 {
 118         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 119         u64 val = irq->intid;
 120
 121         if (irq->pending) {
 122                 val |= ICH_LR_PENDING_BIT;
 123
 124                 if (irq->config == VGIC_CONFIG_EDGE)
 125                         irq->pending = false;
 126
 127                 if (vgic_irq_is_sgi(irq->intid) &&
 128                     model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 129                         u32 src = ffs(irq->source);
 130
 131                         BUG_ON(!src);
 132                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 133                         irq->source &= ~(1 << (src - 1));
 134                         if (irq->source)
 135                                 irq->pending = true;
 136                 }
 137         }
 138
 139         if (irq->active)
 140                 val |= ICH_LR_ACTIVE_BIT;
 141
 142         if (irq->hw) {
 143                 val |= ICH_LR_HW;
 144                 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
 145         } else {
 146                 if (irq->config == VGIC_CONFIG_LEVEL)
 147                         val |= ICH_LR_EOI;
 148         }
 149
 150         /*
 151          * We currently only support Group1 interrupts, which is a
 152          * known defect. This needs to be addressed at some point.
 153          */
 154         if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
 155                 val |= ICH_LR_GROUP;
 156
 157         val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
 158
 159         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
 160 }
 161
 162 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
 163 {
 164         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
 165 }
 166
 167 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 168 {
 169         u32 vmcr;
 170
 171         vmcr  = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
 172         vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
 173         vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
 174         vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
 175
 176         vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
 177 }
 178
 179 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 180 {
 181         u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
 182
 183         vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
 184         vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
 185         vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
 186         vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
 187 }
 188
 189 void vgic_v3_enable(struct kvm_vcpu *vcpu)
 190 {
 191         struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
 192
 193         /*
 194          * By forcing VMCR to zero, the GIC will restore the binary
 195          * points to their reset values. Anything else resets to zero
 196          * anyway.
 197          */
 198         vgic_v3->vgic_vmcr = 0;
 199         vgic_v3->vgic_elrsr = ~0;
 200
 201         /*
 202          * If we are emulating a GICv3, we do it in an non-GICv2-compatible
 203          * way, so we force SRE to 1 to demonstrate this to the guest.
 204          * This goes with the spec allowing the value to be RAO/WI.
 205          */
 206         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
 207                 vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
 208         else
 209                 vgic_v3->vgic_sre = 0;
 210
 211         /* Get the show on the road... */
 212         vgic_v3->vgic_hcr = ICH_HCR_EN;
 213 }
 214
 215 /* check for overlapping regions and for regions crossing the end of memory */
 216 static bool vgic_v3_check_base(struct kvm *kvm)
 217 {
 218         struct vgic_dist *d = &kvm->arch.vgic;
 219         gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
 220
 221         redist_size *= atomic_read(&kvm->online_vcpus);
 222
 223         if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
 224                 return false;
 225         if (d->vgic_redist_base + redist_size < d->vgic_redist_base)
 226                 return false;
 227
 228         if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
 229                 return true;
 230         if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
 231                 return true;
 232
 233         return false;
 234 }
 235
 236 int vgic_v3_map_resources(struct kvm *kvm)
 237 {
 238         int ret = 0;
 239         struct vgic_dist *dist = &kvm->arch.vgic;
 240
 241         if (vgic_ready(kvm))
 242                 goto out;
 243
 244         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 245             IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
 246                 kvm_err("Need to set vgic distributor addresses first\n");
 247                 ret = -ENXIO;
 248                 goto out;
 249         }
 250
 251         if (!vgic_v3_check_base(kvm)) {
 252                 kvm_err("VGIC redist and dist frames overlap\n");
 253                 ret = -EINVAL;
 254                 goto out;
 255         }
 256
 257         /*
 258          * For a VGICv3 we require the userland to explicitly initialize
 259          * the VGIC before we need to use it.
 260          */
 261         if (!vgic_initialized(kvm)) {
 262                 ret = -EBUSY;
 263                 goto out;
 264         }
 265
 266         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
 267         if (ret) {
 268                 kvm_err("Unable to register VGICv3 dist MMIO regions\n");
 269                 goto out;
 270         }
 271
 272         ret = vgic_register_redist_iodevs(kvm, dist->vgic_redist_base);
 273         if (ret) {
 274                 kvm_err("Unable to register VGICv3 redist MMIO regions\n");
 275                 goto out;
 276         }
 277
 278         dist->ready = true;
 279
 280 out:
 281         if (ret)
 282                 kvm_vgic_destroy(kvm);
 283         return ret;
 284 }
 285
 286 /**
 287  * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
 288  * @node:       pointer to the DT node
 289  *
 290  * Returns 0 if a GICv3 has been found, returns an error code otherwise
 291  */
 292 int vgic_v3_probe(const struct gic_kvm_info *info)
 293 {
 294         u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
 295
 296         /*
 297          * The ListRegs field is 5 bits, but there is a architectural
 298          * maximum of 16 list registers. Just ignore bit 4...
 299          */
 300         kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
 301         kvm_vgic_global_state.can_emulate_gicv2 = false;
 302
 303         if (!info->vcpu.start) {
 304                 kvm_info("GICv3: no GICV resource entry\n");
 305                 kvm_vgic_global_state.vcpu_base = 0;
 306         } else if (!PAGE_ALIGNED(info->vcpu.start)) {
 307                 pr_warn("GICV physical address 0x%llx not page aligned\n",
 308                         (unsigned long long)info->vcpu.start);
 309                 kvm_vgic_global_state.vcpu_base = 0;
 310         } else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
 311                 pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
 312                         (unsigned long long)resource_size(&info->vcpu),
 313                         PAGE_SIZE);
 314                 kvm_vgic_global_state.vcpu_base = 0;
 315         } else {
 316                 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 317                 kvm_vgic_global_state.can_emulate_gicv2 = true;
 318                 kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 319                 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
 320         }
 321         if (kvm_vgic_global_state.vcpu_base == 0)
 322                 kvm_info("disabling GICv2 emulation\n");
 323         kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
 324
 325         kvm_vgic_global_state.vctrl_base = NULL;
 326         kvm_vgic_global_state.type = VGIC_V3;
 327         kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
 328
 329         return 0;
 330 }