/dts-v1/;

#include "skeleton.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	model = "Qualcomm APQ8064";
	compatible = "qcom,apq8064";
	interrupt-parent = <&intc>;

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		smem_region: smem@80000000 {
			reg = <0x80000000 0x200000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
			clocks = <&kraitcc 0>, <&kraitcc 4>;
			clock-names = "cpu", "l2";
			clock-latency = <100000>;
			cooling-min-level = <0>;
			cooling-max-level = <7>;
			#cooling-cells = <2>;
		};

		CPU1: cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
			clocks = <&kraitcc 1>, <&kraitcc 4>;
			clock-names = "cpu", "l2";
			clock-latency = <100000>;
			cooling-min-level = <0>;
			cooling-max-level = <7>;
			#cooling-cells = <2>;
		};

		CPU2: cpu@2 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
			clocks = <&kraitcc 2>, <&kraitcc 4>;
			clock-names = "cpu", "l2";
			clock-latency = <100000>;
			cooling-min-level = <0>;
			cooling-max-level = <7>;
			#cooling-cells = <2>;
		};

		CPU3: cpu@3 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
			clocks = <&kraitcc 3>, <&kraitcc 4>;
			clock-names = "cpu", "l2";
			clock-latency = <100000>;
			cooling-min-level = <0>;
			cooling-max-level = <7>;
			#cooling-cells = <2>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};

		qcom,l2 {
			qcom,l2-rates = <384000000 972000000 1188000000>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <400>;
				exit-latency-us = <900>;
				min-residency-us = <3000>;
			};
		};
	};

	thermal-zones {
		cpu-thermal0 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 7>;

			trips {
				cpu_alert0: trip@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit0: trip@1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		cpu-thermal1 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 8>;

			trips {
				cpu_alert1: trip@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit1: trip@1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert1>;
					cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		cpu-thermal2 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 9>;

			trips {
				cpu_alert2: trip@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit2: trip@1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert2>;
					cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		cpu-thermal3 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 10>;

			trips {
				cpu_alert3: trip@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit3: trip@1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert3>;
					cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	thermal-zones {
		cpu-thermal0 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&gcc 7>;

			trips {
				cpu_alert0: trip@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit0: trip@1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu-thermal1 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&gcc 8>;

			trips {
				cpu_alert1: trip@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit1: trip@1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu-thermal2 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&gcc 9>;

			trips {
				cpu_alert2: trip@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit2: trip@1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu-thermal3 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&gcc 10>;

			trips {
				cpu_alert3: trip@0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit3: trip@1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 10 0x304>;
	};

	clocks {
		cxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		pxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <27000000>;
		};

		sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	sfpb_mutex: hwmutex {
		compatible = "qcom,sfpb-mutex";
		syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
		#hwlock-cells = <1>;
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_region>;

		hwlocks = <&sfpb_mutex 3>;
	};

	qcom,pvs {
		qcom,pvs-format-a;
		qcom,speed0-pvs0-bin-v0 =
			< 384000000 950000  >,
			< 486000000 975000  >,
			< 594000000 1000000  >,
			< 702000000 1025000  >,
			< 810000000 1075000  >,
			< 918000000 1100000  >,
			< 1026000000 1125000 >,
			< 1080000000 1175000 >,
			< 1134000000 1175000 >,
			< 1188000000 1200000 >,
			< 1242000000 1200000 >,
			< 1296000000 1225000 >,
			< 1350000000 1225000 >,
			< 1404000000 1237500 >,
			< 1458000000 1237500 >,
			< 1512000000 1250000 >;

		qcom,speed0-pvs1-bin-v0 =
			< 384000000 900000  >,
			< 486000000 925000  >,
			< 594000000 950000  >,
			< 702000000 975000  >,
			< 810000000 1025000  >,
			< 918000000 1050000  >,
			< 1026000000 1075000 >,
			< 1080000000 1125000 >,
			< 1134000000 1125000 >,
			< 1188000000 1150000 >,
			< 1242000000 1150000 >,
			< 1296000000 1175000 >,
			< 1350000000 1175000 >,
			< 1404000000 1187500 >,
			< 1458000000 1187500 >,
			< 1512000000 1200000 >;

		qcom,speed0-pvs3-bin-v0 =
			< 384000000 850000  >,
			< 486000000 875000  >,
			< 594000000 900000  >,
			< 702000000 925000  >,
			< 810000000 975000  >,
			< 918000000 1000000  >,
			< 1026000000 1025000 >,
			< 1080000000 1075000 >,
			< 1134000000 1075000 >,
			< 1188000000 1100000 >,
			< 1242000000 1100000 >,
			< 1296000000 1125000 >,
			< 1350000000 1125000 >,
			< 1404000000 1137500 >,
			< 1458000000 1137500 >,
			< 1512000000 1150000 >;

		qcom,speed0-pvs4-bin-v0 =
			< 384000000 850000  >,
			< 486000000 875000  >,
			< 594000000 900000  >,
			< 702000000 925000  >,
			< 810000000 962500  >,
			< 918000000 975000  >,
			< 1026000000 1000000 >,
			< 1080000000 1050000 >,
			< 1134000000 1050000 >,
			< 1188000000 1075000 >,
			< 1242000000 1075000 >,
			< 1296000000 1100000 >,
			< 1350000000 1100000 >,
			< 1404000000 1112500 >,
			< 1458000000 1112500 >,
			< 1512000000 1125000 >;

		qcom,speed1-pvs0-bin-v0 =
			< 384000000 950000  >,
			< 486000000 950000  >,
			< 594000000 950000  >,
			< 702000000 962500  >,
			< 810000000 1000000  >,
			< 918000000 1025000  >,
			< 1026000000 1037500 >,
			< 1134000000 1075000 >,
			< 1242000000 1087500 >,
			< 1350000000 1125000 >,
			< 1458000000 1150000 >,
			< 1566000000 1175000 >,
			< 1674000000 1225000 >,
			< 1728000000 1250000 >;

		qcom,speed1-pvs1-bin-v0 =
			< 384000000 950000  >,
			< 486000000 950000  >,
			< 594000000 950000  >,
			< 702000000 962500  >,
			< 810000000 975000  >,
			< 918000000 1000000 >,
			< 1026000000 1012500 >,
			< 1134000000 1037500 >,
			< 1242000000 1050000 >,
			< 1350000000 1087500 >,
			< 1458000000 1112500 >,
			< 1566000000 1150000 >,
			< 1674000000 1187500 >,
			< 1728000000 1200000 >;

		qcom,speed1-pvs2-bin-v0 =
			< 384000000 925000  >,
			< 486000000 925000  >,
			< 594000000 925000  >,
			< 702000000 925000  >,
			< 810000000 937500  >,
			< 918000000 950000  >,
			< 1026000000 975000 >,
			< 1134000000 1000000 >,
			< 1242000000 1012500 >,
			< 1350000000 1037500 >,
			< 1458000000 1075000 >,
			< 1566000000 1100000 >,
			< 1674000000 1137500 >,
			< 1728000000 1162500 >;

		qcom,speed1-pvs3-bin-v0 =
			< 384000000 900000  >,
			< 486000000 900000  >,
			< 594000000 900000  >,
			< 702000000 900000  >,
			< 810000000 900000  >,
			< 918000000 925000  >,
			< 1026000000 950000 >,
			< 1134000000 975000 >,
			< 1242000000 987500 >,
			< 1350000000 1000000 >,
			< 1458000000 1037500 >,
			< 1566000000 1062500 >,
			< 1674000000 1100000 >,
			< 1728000000 1125000 >;

		qcom,speed1-pvs4-bin-v0 =
			< 384000000 875000  >,
			< 486000000 875000  >,
			< 594000000 875000  >,
			< 702000000 875000  >,
			< 810000000 887500  >,
			< 918000000 900000  >,
			< 1026000000 925000 >,
			< 1134000000 950000 >,
			< 1242000000 962500 >,
			< 1350000000 975000 >,
			< 1458000000 1000000 >,
			< 1566000000 1037500 >,
			< 1674000000 1075000 >,
			< 1728000000 1100000 >;

		qcom,speed1-pvs5-bin-v0 =
			< 384000000 875000  >,
			< 486000000 875000  >,
			< 594000000 875000  >,
			< 702000000 875000  >,
			< 810000000 887500  >,
			< 918000000 900000  >,
			< 1026000000 925000 >,
			< 1134000000 937500 >,
			< 1242000000 950000 >,
			< 1350000000 962500 >,
			< 1458000000 987500 >,
			< 1566000000 1012500 >,
			< 1674000000 1050000 >,
			< 1728000000 1075000 >;

		qcom,speed1-pvs6-bin-v0 =
			< 384000000 875000  >,
			< 486000000 875000  >,
			< 594000000 875000  >,
			< 702000000 875000  >,
			< 810000000 887500  >,
			< 918000000 900000  >,
			< 1026000000 925000 >,
			< 1134000000 937500 >,
			< 1242000000 950000 >,
			< 1350000000 962500 >,
			< 1458000000 975000 >,
			< 1566000000 1000000 >,
			< 1674000000 1025000 >,
			< 1728000000 1050000 >;

		qcom,speed2-pvs0-bin-v0 =
			< 384000000 950000  >,
			< 486000000 950000  >,
			< 594000000 950000  >,
			< 702000000 950000  >,
			< 810000000 962500  >,
			< 918000000 975000  >,
			< 1026000000 1000000 >,
			< 1134000000 1025000 >,
			< 1242000000 1037500 >,
			< 1350000000 1062500 >,
			< 1458000000 1100000 >,
			< 1566000000 1125000 >,
			< 1674000000 1175000 >,
			< 1782000000 1225000 >,
			< 1890000000 1287500 >;

		qcom,speed2-pvs1-bin-v0 =
			< 384000000 925000  >,
			< 486000000 925000  >,
			< 594000000 925000  >,
			< 702000000 925000  >,
			< 810000000 937500  >,
			< 918000000 950000  >,
			< 1026000000 975000 >,
			< 1134000000 1000000 >,
			< 1242000000 1012500 >,
			< 1350000000 1037500 >,
			< 1458000000 1075000 >,
			< 1566000000 1100000 >,
			< 1674000000 1137500 >,
			< 1782000000 1187500 >,
			< 1890000000 1250000 >;

		qcom,speed2-pvs2-bin-v0 =
			< 384000000 900000  >,
			< 486000000 900000  >,
			< 594000000 900000  >,
			< 702000000 900000  >,
			< 810000000 912500  >,
			< 918000000 925000  >,
			< 1026000000 950000 >,
			< 1134000000 975000 >,
			< 1242000000 987500 >,
			< 1350000000 1012500 >,
			< 1458000000 1050000 >,
			< 1566000000 1075000 >,
			< 1674000000 1112500 >,
			< 1782000000 1162500 >,
			< 1890000000 1212500 >;

		qcom,speed2-pvs3-bin-v0 =
			< 384000000 900000  >,
			< 486000000 900000  >,
			< 594000000 900000  >,
			< 702000000 900000  >,
			< 810000000 900000  >,
			< 918000000 912500  >,
			< 1026000000 937500 >,
			< 1134000000 962500 >,
			< 1242000000 975000 >,
			< 1350000000 1000000 >,
			< 1458000000 1025000 >,
			< 1566000000 1050000 >,
			< 1674000000 1087500 >,
			< 1782000000 1137500 >,
			< 1890000000 1175000 >;

		qcom,speed2-pvs4-bin-v0 =
			< 384000000 875000  >,
			< 486000000 875000  >,
			< 594000000 875000  >,
			< 702000000 875000  >,
			< 810000000 887500  >,
			< 918000000 900000  >,
			< 1026000000 925000 >,
			< 1134000000 950000 >,
			< 1242000000 962500 >,
			< 1350000000 975000 >,
			< 1458000000 1000000 >,
			< 1566000000 1037500 >,
			< 1674000000 1075000 >,
			< 1782000000 1112500 >,
			< 1890000000 1150000 >;

		qcom,speed2-pvs5-bin-v0 =
			< 384000000 875000  >,
			< 486000000 875000  >,
			< 594000000 875000  >,
			< 702000000 875000  >,
			< 810000000 887500  >,
			< 918000000 900000  >,
			< 1026000000 925000 >,
			< 1134000000 937500 >,
			< 1242000000 950000 >,
			< 1350000000 962500 >,
			< 1458000000 987500 >,
			< 1566000000 1012500 >,
			< 1674000000 1050000 >,
			< 1782000000 1087500 >,
			< 1890000000 1125000 >;

		qcom,speed2-pvs6-bin-v0 =
			< 384000000 875000  >,
			< 486000000 875000  >,
			< 594000000 875000  >,
			< 702000000 875000  >,
			< 810000000 887500  >,
			< 918000000 900000  >,
			< 1026000000 925000 >,
			< 1134000000 937500 >,
			< 1242000000 950000 >,
			< 1350000000 962500 >,
			< 1458000000 975000 >,
			< 1566000000 1000000 >,
			< 1674000000 1025000 >,
			< 1782000000 1062500 >,
			< 1890000000 1100000 >;

		qcom,speed14-pvs0-bin-v0 =
			< 384000000 950000 >,
			< 486000000 950000 >,
			< 594000000 950000 >,
			< 702000000 962500 >,
			< 810000000 1000000 >,
			< 918000000 1025000 >,
			< 1026000000 1037500 >,
			< 1134000000 1075000 >,
			< 1242000000 1087500 >,
			< 1350000000 1125000 >,
			< 1458000000 1150000 >,
			< 1512000000 1162500 >;

		qcom,speed14-pvs1-bin-v0 =
			< 384000000 950000 >,
			< 486000000 950000 >,
			< 594000000 950000 >,
			< 702000000 962500 >,
			< 810000000 975000 >,
			< 918000000 1000000 >,
			< 1026000000 1012500 >,
			< 1134000000 1037500 >,
			< 1242000000 1050000 >,
			< 1350000000 1087500 >,
			< 1458000000 1112500 >,
			< 1512000000 1125000 >;

		qcom,speed14-pvs2-bin-v0 =
			< 384000000 925000 >,
			< 486000000 925000 >,
			< 594000000 925000 >,
			< 702000000 925000 >,
			< 810000000 937500 >,
			< 918000000 950000 >,
			< 1026000000 975000 >,
			< 1134000000 1000000 >,
			< 1242000000 1012500 >,
			< 1350000000 1037500 >,
			< 1458000000 1075000 >,
			< 1512000000 1087500 >;

		qcom,speed14-pvs3-bin-v0 =
			< 384000000 900000 >,
			< 486000000 900000 >,
			< 594000000 900000 >,
			< 702000000 900000 >,
			< 810000000 900000 >,
			< 918000000 925000 >,
			< 1026000000 950000 >,
			< 1134000000 975000 >,
			< 1242000000 987500 >,
			< 1350000000 1000000 >,
			< 1458000000 1037500 >,
			< 1512000000 1050000 >;

		qcom,speed14-pvs4-bin-v0 =
			< 384000000 875000 >,
			< 486000000 875000 >,
			< 594000000 875000 >,
			< 702000000 875000 >,
			< 810000000 887500 >,
			< 918000000 900000 >,
			< 1026000000 925000 >,
			< 1134000000 950000 >,
			< 1242000000 962500 >,
			< 1350000000 975000 >,
			< 1458000000 1000000 >,
			< 1512000000 1012500 >;

		qcom,speed14-pvs5-bin-v0 =
			< 384000000 875000 >,
			< 486000000 875000 >,
			< 594000000 875000 >,
			< 702000000 875000 >,
			< 810000000 887500 >,
			< 918000000 900000 >,
			< 1026000000 925000 >,
			< 1134000000 937500 >,
			< 1242000000 950000 >,
			< 1350000000 962500 >,
			< 1458000000 987500 >,
			< 1512000000 1000000 >;

		qcom,speed14-pvs6-bin-v0 =
			< 384000000 875000 >,
			< 486000000 875000 >,
			< 594000000 875000 >,
			< 702000000 875000 >,
			< 810000000 887500 >,
			< 918000000 900000 >,
			< 1026000000 925000 >,
			< 1134000000 937500 >,
			< 1242000000 950000 >,
			< 1350000000 962500 >,
			< 1458000000 975000 >,
			< 1512000000 987500 >;
	};

	kraitcc: clock-controller {
		compatible = "qcom,krait-cc-v1";
		#clock-cells = <1>;
	};

	clocks {
		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			#clock-cells = <0>;
		};
	};

	clocks {
		cxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		pxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <27000000>;
		};

		sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		tlmm_pinmux: pinctrl@800000 {
			compatible = "qcom,apq8064-pinctrl";
			reg = <0x800000 0x4000>;

			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;

			pinctrl-names = "default";
			pinctrl-0 = <&ps_hold>;

			sdc4_gpios: sdc4-gpios {
				pios {
					pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
					function = "sdc4";
				};
			};

			hdmi_pinctrl: hdmi-pinctrl {
				mux1 {
					pins = "gpio69", "gpio70", "gpio71";
					function = "hdmi";
					bias-pull-up;
					drive-strength = <2>;
				};
				mux2 {
					pins = "gpio72";
					function = "hdmi";
					bias-pull-down;
					drive-strength = <16>;
				};
			};
			ps_hold: ps_hold {
				mux {
					pins = "gpio78";
					function = "ps_hold";
				};
			};

			i2c1_pins: i2c1 {
				mux {
					pins = "gpio20", "gpio21";
					function = "gsbi1";
				};
			};

			i2c3_pins: i2c3 {
				mux {
					pins = "gpio8", "gpio9";
					function = "gsbi3";
				};
			};

			gsbi6_uart_2pins: gsbi6_uart_2pins {
				mux {
					pins = "gpio14", "gpio15";
					function = "gsbi6";
				};
			};

			gsbi6_uart_4pins: gsbi6_uart_4pins {
				mux {
					pins = "gpio14", "gpio15", "gpio16", "gpio17";
					function = "gsbi6";
				};
			};

			gsbi7_uart_2pins: gsbi7_uart_2pins {
				mux {
					pins = "gpio82", "gpio83";
					function = "gsbi7";
				};
			};

			gsbi7_uart_4pins: gsbi7_uart_4pins {
				mux {
					pins = "gpio82", "gpio83", "gpio84", "gpio85";
					function = "gsbi7";
				};
			};
		};

		sfpb_wrapper_mutex: syscon@1200000 {
			compatible = "syscon";
			reg = <0x01200000 0x8000>;
		};

		intc: interrupt-controller@2000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x02000000 0x1000>,
			      <0x02002000 0x1000>;
		};

		timer@200a000 {
			compatible = "qcom,kpss-timer", "qcom,msm-timer";
			interrupts = <1 1 0x301>,
				     <1 2 0x301>,
				     <1 3 0x301>;
			reg = <0x0200a000 0x100>;
			clock-frequency = <27000000>,
					  <32768>;
			cpu-offset = <0x80000>;
		};

		watchdog@208a038 {
			compatible = "qcom,kpss-wdt-apq8064";
			reg = <0x0208a038 0x40>;
			clocks = <&sleep_clk>;
			timeout-sec = <10>;
		};

		acc0: clock-controller@2088000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
			clock-output-names = "acpu0_aux";
		};

		acc1: clock-controller@2098000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
			clock-output-names = "acpu1_aux";
		};

		acc2: clock-controller@20a8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
			clock-output-names = "acpu2_aux";
		};

		acc3: clock-controller@20b8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
			clock-output-names = "acpu3_aux";
		};

		saw0: power-controller@2089000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
			regulator;
			regulator-name = "krait0";
			regulator-always-on;
			regulator-min-microvolt = <825000>;
			regulator-max-microvolt = <1250000>;
		};

		saw1: power-controller@2099000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
			regulator;
			regulator-name = "krait1";
			regulator-always-on;
			regulator-min-microvolt = <825000>;
			regulator-max-microvolt = <1250000>;
		};

		saw2: power-controller@20a9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
			regulator;
			regulator-name = "krait2";
			regulator-always-on;
			regulator-min-microvolt = <825000>;
			regulator-max-microvolt = <1250000>;
		};

		saw3: power-controller@20b9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
			regulator;
			regulator-name = "krait3";
			regulator-always-on;
			regulator-min-microvolt = <825000>;
			regulator-max-microvolt = <1250000>;
		};

		gsbi1: gsbi@12440000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <1>;
			reg = <0x12440000 0x100>;
			clocks = <&gcc GSBI1_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			i2c1: i2c@12460000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				pinctrl-0 = <&i2c1_pins>;
				pinctrl-names = "default";
				reg = <0x12460000 0x1000>;
				interrupts = <0 194 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi2: gsbi@12480000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <2>;
			reg = <0x12480000 0x100>;
			clocks = <&gcc GSBI2_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			i2c2: i2c@124a0000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x124a0000 0x1000>;
				interrupts = <0 196 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi3: gsbi@16200000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <3>;
			reg = <0x16200000 0x100>;
			clocks = <&gcc GSBI3_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			i2c3: i2c@16280000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				pinctrl-0 = <&i2c3_pins>;
				pinctrl-names = "default";
				reg = <0x16280000 0x1000>;
				interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
				clocks = <&gcc GSBI3_QUP_CLK>,
					 <&gcc GSBI3_H_CLK>;
				clock-names = "core", "iface";
			};
		};

		gsbi5: gsbi@1a200000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <5>;
			reg = <0x1a200000 0x03>;
			clocks = <&gcc GSBI5_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gsbi5_serial: serial@1a240000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x1a240000 0x100>,
				      <0x1a200000 0x03>;
				interrupts = <0 154 0x0>;
				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		gsbi6: gsbi@16500000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <6>;
			reg = <0x16500000 0x03>;
			clocks = <&gcc GSBI6_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			syscon-tcsr = <&tcsr>;

			gsbi6_serial: serial@16540000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16540000 0x100>,
				      <0x16500000 0x03>;
				interrupts = <0 156 0x0>;
				clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
				clock-names = "core", "iface";

				qcom,rx-crci = <11>;
				qcom,tx-crci = <6>;

				dmas = <&adm 6>, <&adm 7>;
				dma-names = "rx", "tx";

				status = "disabled";
			};
		};

		gsbi7: gsbi@16600000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <7>;
			reg = <0x16600000 0x100>;
			clocks = <&gcc GSBI7_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			syscon-tcsr = <&tcsr>;

			gsbi7_serial: serial@16640000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16640000 0x1000>,
				      <0x16600000 0x1000>;
				interrupts = <0 158 0x0>;
				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		rng@1a500000 {
			compatible = "qcom,prng";
			reg = <0x1a500000 0x200>;
			clocks = <&gcc PRNG_CLK>;
			clock-names = "core";
		};

		qcom,ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x00500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";

			pmicintc: pmic@0 {
				compatible = "qcom,pm8921";
				interrupt-parent = <&tlmm_pinmux>;
				interrupts = <74 8>;
				#interrupt-cells = <2>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <0>;

				pm8921_gpio: gpio@150 {

					compatible = "qcom,pm8921-gpio",
						     "qcom,ssbi-gpio";
					reg = <0x150>;
					interrupts = <192 1>, <193 1>, <194 1>,
						     <195 1>, <196 1>, <197 1>,
						     <198 1>, <199 1>, <200 1>,
						     <201 1>, <202 1>, <203 1>,
						     <204 1>, <205 1>, <206 1>,
						     <207 1>, <208 1>, <209 1>,
						     <210 1>, <211 1>, <212 1>,
						     <213 1>, <214 1>, <215 1>,
						     <216 1>, <217 1>, <218 1>,
						     <219 1>, <220 1>, <221 1>,
						     <222 1>, <223 1>, <224 1>,
						     <225 1>, <226 1>, <227 1>,
						     <228 1>, <229 1>, <230 1>,
						     <231 1>, <232 1>, <233 1>,
						     <234 1>, <235 1>;

					gpio-controller;
					#gpio-cells = <2>;

				};

				pm8921_mpps: mpps@50 {
					compatible = "qcom,pm8921-mpp",
						     "qcom,ssbi-mpp";
					reg = <0x50>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupts =
					<128 1>, <129 1>, <130 1>, <131 1>,
					<132 1>, <133 1>, <134 1>, <135 1>,
					<136 1>, <137 1>, <138 1>, <139 1>;
				};

				rtc@11d {
					compatible = "qcom,pm8921-rtc";
					interrupt-parent = <&pmicintc>;
					interrupts = <39 1>;
					reg = <0x11d>;
					allow-set-time;
				};

				pwrkey@1c {
					compatible = "qcom,pm8921-pwrkey";
					reg = <0x1c>;
					interrupt-parent = <&pmicintc>;
					interrupts = <50 1>, <51 1>;
					debounce = <15625>;
					pull-up;
				};
			};
		};

		qfprom: qfprom@00700000 {
			compatible	= "qcom,qfprom";
			reg		= <0x00700000 0x1000>;
			#address-cells	= <1>;
			#size-cells	= <1>;
			ranges;
			tsens_calib: calib {
				reg = <0x404 0x10>;
			};
			tsens_backup: backup_calib {
				reg = <0x414 0x10>;
			};
		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-apq8064";
			reg = <0x00900000 0x4000>;
			nvmem-cells = <&tsens_calib>, <&tsens_backup>;
			nvmem-cell-names = "calib", "calib_backup";
			qcom,tsens-slopes = <1176 1176 1154 1176 1111
				1132 1132 1199 1132 1199 1132>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#thermal-sensor-cells = <1>;
		};

		lcc: clock-controller@28000000 {
			compatible = "qcom,lcc-apq8064";
			reg = <0x28000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		mmcc: clock-controller@4000000 {
			compatible = "qcom,mmcc-apq8064";
			reg = <0x4000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		l2cc: clock-controller@2011000 {
			compatible	= "syscon";
			reg		= <0x2011000 0x1000>;
		};

		rpm@108000 {
			compatible	= "qcom,rpm-apq8064";
			reg		= <0x108000 0x1000>;
			qcom,ipc	= <&l2cc 0x8 2>;

			interrupts	= <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
					  <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			interrupt-names	= "ack", "err", "wakeup";

			rpmcc: clock-controller {
				compatible	= "qcom,rpmcc-apq8064", "qcom,rpmcc";
				#clock-cells = <1>;
			};

			regulators {
				compatible = "qcom,rpm-pm8921-regulators";

				pm8921_s1: s1 {};
				pm8921_s2: s2 {};
				pm8921_s3: s3 {};
				pm8921_s4: s4 {};
				pm8921_s7: s7 {};
				pm8921_s8: s8 {};

				pm8921_l1: l1 {};
				pm8921_l2: l2 {};
				pm8921_l3: l3 {};
				pm8921_l4: l4 {};
				pm8921_l5: l5 {};
				pm8921_l6: l6 {};
				pm8921_l7: l7 {};
				pm8921_l8: l8 {};
				pm8921_l9: l9 {};
				pm8921_l10: l10 {};
				pm8921_l11: l11 {};
				pm8921_l12: l12 {};
				pm8921_l14: l14 {};
				pm8921_l15: l15 {};
				pm8921_l16: l16 {};
				pm8921_l17: l17 {};
				pm8921_l18: l18 {};
				pm8921_l21: l21 {};
				pm8921_l22: l22 {};
				pm8921_l23: l23 {};
				pm8921_l24: l24 {};
				pm8921_l25: l25 {};
				pm8921_l26: l26 {};
				pm8921_l27: l27 {};
				pm8921_l28: l28 {};
				pm8921_l29: l29 {};

				pm8921_lvs1: lvs1 {};
				pm8921_lvs2: lvs2 {};
				pm8921_lvs3: lvs3 {};
				pm8921_lvs4: lvs4 {};
				pm8921_lvs5: lvs5 {};
				pm8921_lvs6: lvs6 {};
				pm8921_lvs7: lvs7 {};

				pm8921_usb_switch: usb-switch {};

				pm8921_hdmi_switch: hdmi-switch {
					bias-pull-down;
				};

				pm8921_ncp: ncp {};
			};
		};

		usb1_phy: phy@12500000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12500000 0x400>;
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS1_XCVR_CLK>,
					  <&gcc USB_HS1_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS1_RESET>;
			reset-names	= "link";
		};

		usb3_phy: phy@12520000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12520000 0x400>;
			interrupts	= <GIC_SPI 188 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS3_XCVR_CLK>,
					  <&gcc USB_HS3_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS3_RESET>;
			reset-names	= "link";
		};

		usb4_phy: phy@12530000 {
			compatible	= "qcom,usb-otg-ci";
			reg		= <0x12530000 0x400>;
			interrupts	= <GIC_SPI 215 IRQ_TYPE_NONE>;
			status		= "disabled";
			dr_mode		= "host";

			clocks		= <&gcc USB_HS4_XCVR_CLK>,
					  <&gcc USB_HS4_H_CLK>;
			clock-names	= "core", "iface";

			resets		= <&gcc USB_HS4_RESET>;
			reset-names	= "link";
		};

		gadget1: gadget@12500000 {
			compatible	= "qcom,ci-hdrc";
			reg		= <0x12500000 0x400>;
			status		= "disabled";
			dr_mode		= "peripheral";
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			usb-phy		= <&usb1_phy>;
		};

		usb1: usb@12500000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12500000 0x400>;
			interrupts	= <GIC_SPI 100 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb1_phy>;
		};

		usb3: usb@12520000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12520000 0x400>;
			interrupts	= <GIC_SPI 188 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb3_phy>;
		};

		usb4: usb@12530000 {
			compatible	= "qcom,ehci-host";
			reg		= <0x12530000 0x400>;
			interrupts	= <GIC_SPI 215 IRQ_TYPE_NONE>;
			status		= "disabled";
			usb-phy		= <&usb4_phy>;
		};

		sata_phy0: phy@1b400000 {
			compatible	= "qcom,apq8064-sata-phy";
			status		= "disabled";
			reg		= <0x1b400000 0x200>;
			reg-names	= "phy_mem";
			clocks		= <&gcc SATA_PHY_CFG_CLK>;
			clock-names	= "cfg";
			#phy-cells	= <0>;
		};

		sata0: sata@29000000 {
			compatible		= "generic-ahci";
			status			= "disabled";
			reg			= <0x29000000 0x180>;
			interrupts		= <GIC_SPI 209 IRQ_TYPE_NONE>;

			clocks			= <&gcc SFAB_SATA_S_H_CLK>,
						<&gcc SATA_H_CLK>,
						<&gcc SATA_A_CLK>,
						<&gcc SATA_RXOOB_CLK>,
						<&gcc SATA_PMALIVE_CLK>;
			clock-names		= "slave_iface",
						"iface",
						"bus",
						"rxoob",
						"core_pmalive";

			assigned-clocks		= <&gcc SATA_RXOOB_CLK>,
						<&gcc SATA_PMALIVE_CLK>;
			assigned-clock-rates	= <100000000>, <100000000>;

			phys			= <&sata_phy0>;
			phy-names		= "sata-phy";
		};

		/* Temporary fixed regulator */
		sdcc1bam:dma@12402000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12402000 0x8000>;
			interrupts = <0 98 0>;
			clocks = <&gcc SDC1_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc3bam:dma@12182000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12182000 0x8000>;
			interrupts = <0 96 0>;
			clocks = <&gcc SDC3_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc4bam:dma@121c2000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x121c2000 0x8000>;
			interrupts = <0 95 0>;
			clocks = <&gcc SDC4_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		amba {
			compatible = "arm,amba-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			sdcc1: sdcc@12400000 {
				status		= "disabled";
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				reg		= <0x12400000 0x2000>;
				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <8>;
				max-frequency	= <96000000>;
				non-removable;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
				dma-names = "tx", "rx";
			};

			sdcc3: sdcc@12180000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x12180000 0x2000>;
				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <192000000>;
				no-1-8-v;
				dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
				dma-names = "tx", "rx";
			};

			sdcc4: sdcc@121c0000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x121c0000 0x2000>;
				interrupts	= <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <48000000>;
				dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&sdc4_gpios>;
			};
		};

		adm: dma@18320000 {
			compatible = "qcom,adm";
			reg = <0x18320000 0xE0000>;
			interrupts = <GIC_SPI 171 IRQ_TYPE_NONE>;
			#dma-cells = <1>;

			clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
			clock-names = "core", "iface";

			resets = <&gcc ADM0_RESET>,
				 <&gcc ADM0_PBUS_RESET>,
				 <&gcc ADM0_C0_RESET>,
				 <&gcc ADM0_C1_RESET>,
				 <&gcc ADM0_C2_RESET>;
			reset-names = "clk", "pbus", "c0", "c1", "c2";
			qcom,ee = <1>;

			status = "disabled";
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-apq8064", "syscon";
			reg = <0x1a400000 0x100>;
		};

		pcie: pci@1b500000 {
			compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
			reg = <0x1b500000 0x1000
			       0x1b502000 0x80
			       0x1b600000 0x100
			       0x0ff00000 0x100000>;
			reg-names = "dbi", "elbi", "parf", "config";
			device_type = "pci";
			linux,pci-domain = <0>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
				  0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
			interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
			clocks = <&gcc PCIE_A_CLK>,
				 <&gcc PCIE_H_CLK>,
				 <&gcc PCIE_PHY_REF_CLK>;
			clock-names = "core", "iface", "phy";
			resets = <&gcc PCIE_ACLK_RESET>,
				 <&gcc PCIE_HCLK_RESET>,
				 <&gcc PCIE_POR_RESET>,
				 <&gcc PCIE_PCI_RESET>,
				 <&gcc PCIE_PHY_RESET>;
			reset-names = "axi", "ahb", "por", "pci", "phy";
			status = "disabled";
		};

		pil_q6v4: pil@28800000 {
			compatible	= "qcom,tz-pil", "qcom,apq8064-tz-pil";
			qcom,firmware-name = "q6";
			reg		= <0x28800000 0x100>;
			reg-names	= "qdsp6_base";
			qcom,pas-id		= <1>; /* PAS_Q6 */
		};

		smd {
			compatible = "qcom,smd";
			adsp_a11 {
				interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
				qcom,ipc = <&l2cc 8 15>;
				qcom,smd-edge = <1>;
				qcom,remote-pid = <0x2>;
				q6_requests {
					compatible	= "qcom,apr";
					qcom,smd-channels = "apr_audio_svc";
					rproc = <&pil_q6v4>;
				};
			};
		};

		dai_fe: dai_fe {
			compatible	= "qcom,msm-dai-fe";
			#sound-dai-cells = <0>;
		};

		hdmi_dai: dai_hdmi {
			compatible = "qcom,msm-dai-q6-hdmi";
			#sound-dai-cells = <0>;
		};

		hdmi_codec: codec_hdmi {
			compatible = "linux,hdmi-audio";
			#sound-dai-cells = <0>;
		};

		q6_pcm: msm_pcm {
			compatible = "qcom,msm-pcm-dsp";
			#sound-dai-cells = <0>;
		};

		q6_route: msm_pcm_routing {
			compatible = "qcom,msm-pcm-routing";
			#sound-dai-cells = <0>;
		};

		snd {
			compatible	= "qcom,snd-apq8064";
		};


		hdmi: qcom,hdmi-tx@4a00000 {
			compatible = "qcom,hdmi-tx-8960";
			reg-names = "core_physical";
			reg = <0x04a00000 0x1000>;
			interrupts = <GIC_SPI 79 0>;
			clock-names =
			    "core_clk",
			    "master_iface_clk",
			    "slave_iface_clk";
			clocks =
			    <&mmcc HDMI_APP_CLK>,
			    <&mmcc HDMI_M_AHB_CLK>,
			    <&mmcc HDMI_S_AHB_CLK>;
			qcom,hdmi-tx-ddc-clk = <&tlmm_pinmux 70 GPIO_ACTIVE_HIGH>;
			qcom,hdmi-tx-ddc-data = <&tlmm_pinmux 71 GPIO_ACTIVE_HIGH>;
			qcom,hdmi-tx-hpd = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&hdmi_pinctrl>;
		};

		gpu: qcom,adreno-3xx@4300000 {
			compatible = "qcom,adreno-3xx";
			reg = <0x04300000 0x20000>;
			reg-names = "kgsl_3d0_reg_memory";
			interrupts = <GIC_SPI 80 0>;
			interrupt-names = "kgsl_3d0_irq";
			clock-names =
			    "core_clk",
			    "iface_clk",
			    "mem_clk",
			    "mem_iface_clk";
			clocks =
			    <&mmcc GFX3D_CLK>,
			    <&mmcc GFX3D_AHB_CLK>,
			    <&mmcc GFX3D_AXI_CLK>,
			    <&mmcc MMSS_IMEM_AHB_CLK>;
			qcom,chipid = <0x03020002>;

			 iommus = <&gfx3d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
				   &gfx3d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
				   &gfx3d1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
				   &gfx3d1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;

			qcom,gpu-pwrlevels {
				compatible = "qcom,gpu-pwrlevels";
				qcom,gpu-pwrlevel@0 {
					qcom,gpu-freq = <450000000>;
				};
				qcom,gpu-pwrlevel@1 {
					qcom,gpu-freq = <27000000>;
				};
			};
		};

		mdp: qcom,mdp@5100000 {
			compatible = "qcom,mdp";
			reg = <0x05100000 0xf0000>;
			interrupts = <GIC_SPI 75 0>;
			connectors = <&hdmi>;
			gpus = <&gpu>;
			clock-names =
			    "core_clk",
			    "iface_clk",
			    "lut_clk",
			    "src_clk",
			    "hdmi_clk",
			    "mdp_clk",
			    "mdp_axi_clk";
			clocks =
			    <&mmcc MDP_CLK>,
			    <&mmcc MDP_AHB_CLK>,
			    <&mmcc MDP_LUT_CLK>,
			    <&mmcc TV_SRC>,
			    <&mmcc HDMI_TV_CLK>,
			    <&mmcc MDP_TV_CLK>,
			    <&mmcc MDP_AXI_CLK>;

			iommus = <&mdp_port0 0 2
				  &mdp_port1 0 2>;
		};

		mdp_port0: qcom,iommu@7500000 {
			compatible = "qcom,iommu-v0";
			#iommu-cells = <2>;
			clock-names =
			    "smmu_pclk",
			    "iommu_clk";
			clocks =
			    <&mmcc SMMU_AHB_CLK>,
			    <&mmcc MDP_AXI_CLK>;
			reg = <0x07500000 0x100000>;
			interrupts =
			    <GIC_SPI 63 0>,
			    <GIC_SPI 64 0>;
			ncb = <2>;
		};

		mdp_port1: qcom,iommu@7600000 {
			compatible = "qcom,iommu";
			#iommu-cells = <2>;
			clock-names =
			    "smmu_pclk",
			    "iommu_clk";
			clocks =
			    <&mmcc SMMU_AHB_CLK>,
			    <&mmcc MDP_AXI_CLK>;
			reg = <0x07600000 0x100000>;
			interrupts =
			    <GIC_SPI 61 0>,
			    <GIC_SPI 62 0>;
			ncb = <2>;
		};

		gfx3d: qcom,iommu@7c00000 {
			compatible = "qcom,iommu-v0";
			#iommu-cells = <16>;
			clock-names =
			    "smmu_pclk",
			    "iommu_clk";
			clocks =
			    <&mmcc SMMU_AHB_CLK>,
			    <&mmcc GFX3D_AXI_CLK>;
			reg = <0x07c00000 0x100000>;
			interrupts =
			    <GIC_SPI 69 0>,
			    <GIC_SPI 70 0>;
			ncb = <3>;
		};

		gfx3d1: qcom,iommu@7d00000 {
			compatible = "qcom,iommu-v0";
			#iommu-cells = <16>;
			clock-names =
			    "smmu_pclk",
			    "iommu_clk";
			clocks =
			    <&mmcc SMMU_AHB_CLK>,
			    <&mmcc GFX3D_AXI_CLK>;
			reg = <0x07d00000 0x100000>;
			interrupts =
			    <GIC_SPI 210 0>,
			    <GIC_SPI 211 0>;
			ncb = <3>;
		};
	};
};

#include "qcom-apq8064-coresight.dtsi"