- utemp0 = (clkin / op_clk) - 8;
-
- if (i2c->variant->hw == HSI2C_EXYNOS7)
- utemp0 -= t_ftl_cycle;
- else
- utemp0 -= 2 * t_ftl_cycle;
-
- /* CLK_DIV max is 256 */
- for (div = 0; div < 256; div++) {
- utemp1 = utemp0 / (div + 1);
-
- /*
- * SCL_L and SCL_H each has max value of 255
- * Hence, For the clk_cycle to the have right value
- * utemp1 has to be less then 512 and more than 4.
- */
- if ((utemp1 < 512) && (utemp1 > 4)) {
- clk_cycle = utemp1 - 2;
- break;
- } else if (div == 255) {
- dev_warn(i2c->dev, "Failed to calculate divisor");
- return -EINVAL;
- }
+ temp = clkin / op_clk - 8 - t_ftl_cycle;
+ if (i2c->variant->hw != HSI2C_EXYNOS7)
+ temp -= t_ftl_cycle;
+ div = temp / 512;
+ clk_cycle = temp / (div + 1) - 2;
+ if (temp < 4 || div >= 256 || clk_cycle < 2) {
+ dev_warn(i2c->dev, "Failed to calculate divisor");
+ return -EINVAL;