]> git.kernelconcepts.de Git - karo-tx-uboot.git/blobdiff - arch/arm/dts/tegra20.dtsi
Merge branch 'master' of git://git.denx.de/u-boot-arm
[karo-tx-uboot.git] / arch / arm / dts / tegra20.dtsi
index 12049fd6936cbc7c7f7363880eab4e56bc2fd69b..5f927f7e0d4e165babc6b0972140f196a025c60b 100644 (file)
@@ -1,4 +1,8 @@
-/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/tegra20-car.h>
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
 
 / {
        compatible = "nvidia,tegra20";
 
        gpio: gpio@6000d000 {
                compatible = "nvidia,tegra20-gpio";
-               reg = < 0x6000d000 0x1000 >;
-               interrupts = < 64 65 66 67 87 119 121 >;
+               reg = <0x6000d000 0x1000>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
+               #interrupt-cells = <2>;
+               interrupt-controller;
        };
 
        pinmux: pinmux@70000000 {
                dma-channel = < 1 >;
        };
 
-       serial@70006000 {
+       uarta: serial@70006000 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006000 0x40>;
                reg-shift = <2>;
-               interrupts = < 68 >;
+               interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_UARTA>;
+               resets = <&tegra_car 6>;
+               reset-names = "serial";
+               dmas = <&apbdma 8>, <&apbdma 8>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
-       serial@70006040 {
+       uartb: serial@70006040 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006040 0x40>;
                reg-shift = <2>;
-               interrupts = < 69 >;
+               interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_UARTB>;
+               resets = <&tegra_car 7>;
+               reset-names = "serial";
+               dmas = <&apbdma 9>, <&apbdma 9>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
-       serial@70006200 {
+       uartc: serial@70006200 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006200 0x100>;
                reg-shift = <2>;
-               interrupts = < 78 >;
+               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_UARTC>;
+               resets = <&tegra_car 55>;
+               reset-names = "serial";
+               dmas = <&apbdma 10>, <&apbdma 10>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
-       serial@70006300 {
+       uartd: serial@70006300 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006300 0x100>;
                reg-shift = <2>;
-               interrupts = < 122 >;
+               interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_UARTD>;
+               resets = <&tegra_car 65>;
+               reset-names = "serial";
+               dmas = <&apbdma 19>, <&apbdma 19>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
-       serial@70006400 {
+       uarte: serial@70006400 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006400 0x100>;
                reg-shift = <2>;
-               interrupts = < 123 >;
+               interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_UARTE>;
+               resets = <&tegra_car 66>;
+               reset-names = "serial";
+               dmas = <&apbdma 20>, <&apbdma 20>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
        nand: nand-controller@70008000 {
                clocks = <&tegra_car 12>, <&tegra_car 124>;
        };
 
+       spi@7000c380 {
+               compatible = "nvidia,tegra20-sflash";
+               reg = <0x7000c380 0x80>;
+               interrupts = <0 39 0x04>;
+               nvidia,dma-request-selector = <&apbdma 11>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+               /* PERIPH_ID_SPI1, PLLP_OUT0 */
+               clocks = <&tegra_car 43>;
+       };
+
        i2c@7000c400 {
                #address-cells = <1>;
                #size-cells = <0>;
        sdhci@c8000000 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000000 0x200>;
-               interrupts = < 46 >;
+               interrupts = <0 14 0x04>;
+               clocks = <&tegra_car 14>;
+               status = "disabled";
        };
 
        sdhci@c8000200 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000200 0x200>;
-               interrupts = < 47 >;
+               interrupts = <0 15 0x04>;
+               clocks = <&tegra_car 9>;
+               status = "disabled";
        };
 
        sdhci@c8000400 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000400 0x200>;
-               interrupts = < 51 >;
+               interrupts = <0 19 0x04>;
+               clocks = <&tegra_car 69>;
+               status = "disabled";
        };
 
        sdhci@c8000600 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000600 0x200>;
-               interrupts = < 63 >;
+               interrupts = <0 31 0x04>;
+               clocks = <&tegra_car 15>;
+               status = "disabled";
        };
 };