ARM: Implement non-cached memory support

[karo-tx-uboot.git] / arch / arm / lib / cache.c

diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 30686fe69b739af3c04b9902ba01c5ba3fa87e01..9cedeac6d641eb7b8548fb8571bcd6a261388fdb 100644 (file)
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -2,46 +2,94 @@
  * (C) Copyright 2002
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /* for now: just dummy functions to satisfy the linker */
 
 #include <common.h>
+#include <malloc.h>
 
-void  flush_cache (unsigned long dummy1, unsigned long dummy2)
+__weak void flush_cache(unsigned long start, unsigned long size)
 {
-#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
-       void arm1136_cache_flush(void);
+#if defined(CONFIG_CPU_ARM1136)
+
+#if !defined(CONFIG_SYS_ICACHE_OFF)
+       asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */
+#endif
 
-       arm1136_cache_flush();
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+       asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */
 #endif
-#ifdef CONFIG_ARM926EJS
+
+#endif /* CONFIG_CPU_ARM1136 */
+
+#ifdef CONFIG_CPU_ARM926EJS
        /* test and clean, page 2-23 of arm926ejs manual */
        asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
        /* disable write buffer as well (page 2-22) */
        asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-#endif
-#ifdef CONFIG_OMAP34XX
-       void v7_flush_cache_all(void);
+#endif /* CONFIG_CPU_ARM926EJS */
+       return;
+}
 
-       v7_flush_cache_all();
+/*
+ * Default implementation:
+ * do a range flush for the entire range
+ */
+__weak void flush_dcache_all(void)
+{
+       flush_cache(0, ~0);
+}
+
+/*
+ * Default implementation of enable_caches()
+ * Real implementation should be in platform code
+ */
+__weak void enable_caches(void)
+{
+       puts("WARNING: Caches not enabled\n");
+}
+
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+/*
+ * Reserve one MMU section worth of address space below the malloc() area that
+ * will be mapped uncached.
+ */
+static unsigned long noncached_start;
+static unsigned long noncached_end;
+static unsigned long noncached_next;
+
+void noncached_init(void)
+{
+       phys_addr_t start, end;
+       size_t size;
+
+       end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
+       size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
+       start = end - size;
+
+       debug("mapping memory %pa-%pa non-cached\n", &start, &end);
+
+       noncached_start = start;
+       noncached_end = end;
+       noncached_next = start;
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+       mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
 #endif
-       return;
 }
+
+phys_addr_t noncached_alloc(size_t size, size_t align)
+{
+       phys_addr_t next = ALIGN(noncached_next, align);
+
+       if (next >= noncached_end || (noncached_end - next) < size)
+               return 0;
+
+       debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
+       noncached_next = next + size;
+
+       return next;
+}
+#endif /* CONFIG_SYS_NONCACHED_MEMORY */