ARM: PXA3xx: program the CSMSADRCFG register

[karo-tx-linux.git] / arch / arm / mach-pxa / smemc.c

diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c
index 79923058d10f1352d8fd420180fc86ceca06957c..f38aa890b2c915a1114bfe9c6bd281ee3bfdee57 100644 (file)
--- a/arch/arm/mach-pxa/smemc.c
+++ b/arch/arm/mach-pxa/smemc.c
@@ -40,6 +40,8 @@ static void pxa3xx_smemc_resume(void)
        __raw_writel(csadrcfg[1], CSADRCFG1);
        __raw_writel(csadrcfg[2], CSADRCFG2);
        __raw_writel(csadrcfg[3], CSADRCFG3);
+       /* CSMSADRCFG wakes up in its default state (0), so we need to set it */
+       __raw_writel(0x2, CSMSADRCFG);
 }
 
 static struct syscore_ops smemc_syscore_ops = {
@@ -49,8 +51,19 @@ static struct syscore_ops smemc_syscore_ops = {
 
 static int __init smemc_init(void)
 {
-       if (cpu_is_pxa3xx())
+       if (cpu_is_pxa3xx()) {
+               /*
+                * The only documentation we have on the
+                * Chip Select Configuration Register (CSMSADRCFG) is that
+                * it must be programmed to 0x2.
+                * Moreover, in the bit definitions, the second bit
+                * (CSMSADRCFG[1]) is called "SETALWAYS".
+                * Other bits are reserved in this register.
+                */
+               __raw_writel(0x2, CSMSADRCFG);
+
                register_syscore_ops(&smemc_syscore_ops);
+       }
 
        return 0;
 }