x86: Add chromebook_link board

[karo-tx-uboot.git] / arch / x86 / cpu / coreboot / coreboot.c

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 1ce3b5ef6cb48c0add09c12cdd6a08e658255084..85017165c0a8d3215b80335a7136070c525eeaae 100644 (file)
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -3,7 +3,7 @@
  * (C) Copyright 2008
  * Graeme Russ, graeme.russ@gmail.com.
  *
- * SPDX-License-Identifier:    GPL-2.0+ 
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -13,6 +13,7 @@
 #include <ns16550.h>
 #include <asm/msr.h>
 #include <asm/cache.h>
+#include <asm/cpu.h>
 #include <asm/io.h>
 #include <asm/arch-coreboot/tables.h>
 #include <asm/arch-coreboot/sysinfo.h>
@@ -20,18 +21,17 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * Miscellaneous platform dependent initializations
- */
-int cpu_init_f(void)
+int arch_cpu_init(void)
 {
        int ret = get_coreboot_info(&lib_sysinfo);
-       if (ret != 0)
+       if (ret != 0) {
                printf("Failed to parse coreboot tables.\n");
+               return ret;
+       }
 
        timestamp_init();
 
-       return ret;
+       return x86_cpu_init_f();
 }
 
 int board_early_init_f(void)
@@ -73,6 +73,11 @@ void show_boot_progress(int val)
        outb(val, 0x80);
 }
 
+int print_cpuinfo(void)
+{
+       return default_print_cpuinfo();
+}
+
 int last_stage_init(void)
 {
        if (gd->flags & GD_FLG_COLD_BOOT)
@@ -98,7 +103,7 @@ int board_eth_init(bd_t *bis)
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 
-int board_final_cleanup(void)
+void board_final_cleanup(void)
 {
        /* Un-cache the ROM so the kernel has one
         * more MTRR available.
@@ -120,8 +125,6 @@ int board_final_cleanup(void)
        /* Issue SMI to Coreboot to lock down ME and registers */
        printf("Finalizing Coreboot\n");
        outb(0xcb, 0xb2);
-
-       return 0;
 }
 
 void panic_puts(const char *str)