x86: Add a 'pause' instruction in __udelay() for QEMU target

[karo-tx-uboot.git] / arch / x86 / cpu / pci.c

diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index e3993880dbef93b91bda50a2078e9f30369d7a60..f8da08035e62bbcfd5454682bfa5b03fbeca19a9 100644 (file)
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -10,11 +10,15 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <malloc.h>
 #include <pci.h>
+#include <asm/io.h>
 #include <asm/pci.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static struct pci_controller x86_hose;
 
 int pci_early_init_hose(struct pci_controller **hosep)
@@ -27,35 +31,48 @@ int pci_early_init_hose(struct pci_controller **hosep)
 
        board_pci_setup_hose(hose);
        pci_setup_type1(hose);
-       gd->arch.hose = hose;
+       hose->last_busno = pci_hose_scan(hose);
+       gd->hose = hose;
        *hosep = hose;
 
        return 0;
 }
 
+__weak int board_pci_pre_scan(struct pci_controller *hose)
+{
+       return 0;
+}
+
+__weak int board_pci_post_scan(struct pci_controller *hose)
+{
+       return 0;
+}
+
 void pci_init_board(void)
 {
        struct pci_controller *hose = &x86_hose;
 
        /* Stop using the early hose */
-       gd->arch.hose = NULL;
+       gd->hose = NULL;
 
        board_pci_setup_hose(hose);
        pci_setup_type1(hose);
        pci_register_hose(hose);
 
+       board_pci_pre_scan(hose);
        hose->last_busno = pci_hose_scan(hose);
+       board_pci_post_scan(hose);
 }
 
 static struct pci_controller *get_hose(void)
 {
-       if (gd->arch.hose)
-               return gd->arch.hose;
+       if (gd->hose)
+               return gd->hose;
 
        return pci_bus_to_hose(0);
 }
 
-unsigned int pci_read_config8(pci_dev_t dev, unsigned where)
+unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where)
 {
        uint8_t value;
 
@@ -64,7 +81,7 @@ unsigned int pci_read_config8(pci_dev_t dev, unsigned where)
        return value;
 }
 
-unsigned int pci_read_config16(pci_dev_t dev, unsigned where)
+unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where)
 {
        uint16_t value;
 
@@ -73,7 +90,7 @@ unsigned int pci_read_config16(pci_dev_t dev, unsigned where)
        return value;
 }
 
-unsigned int pci_read_config32(pci_dev_t dev, unsigned where)
+unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where)
 {
        uint32_t value;
 
@@ -82,17 +99,85 @@ unsigned int pci_read_config32(pci_dev_t dev, unsigned where)
        return value;
 }
 
-void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
+void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
 {
        pci_hose_write_config_byte(get_hose(), dev, where, value);
 }
 
-void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
+void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
 {
        pci_hose_write_config_word(get_hose(), dev, where, value);
 }
 
-void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
+void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
 {
        pci_hose_write_config_dword(get_hose(), dev, where, value);
 }
+
+int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+                       ulong *valuep, enum pci_size_t size)
+{
+       outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
+       switch (size) {
+       case PCI_SIZE_8:
+               *valuep = inb(PCI_REG_DATA + (offset & 3));
+               break;
+       case PCI_SIZE_16:
+               *valuep = inw(PCI_REG_DATA + (offset & 2));
+               break;
+       case PCI_SIZE_32:
+               *valuep = inl(PCI_REG_DATA);
+               break;
+       }
+
+       return 0;
+}
+
+int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+                        ulong value, enum pci_size_t size)
+{
+       outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
+       switch (size) {
+       case PCI_SIZE_8:
+               outb(value, PCI_REG_DATA + (offset & 3));
+               break;
+       case PCI_SIZE_16:
+               outw(value, PCI_REG_DATA + (offset & 2));
+               break;
+       case PCI_SIZE_32:
+               outl(value, PCI_REG_DATA);
+               break;
+       }
+
+       return 0;
+}
+
+void pci_assign_irqs(int bus, int device, u8 irq[4])
+{
+       pci_dev_t bdf;
+       int func;
+       u16 vendor;
+       u8 pin, line;
+
+       for (func = 0; func < 8; func++) {
+               bdf = PCI_BDF(bus, device, func);
+               vendor = x86_pci_read_config16(bdf, PCI_VENDOR_ID);
+               if (vendor == 0xffff || vendor == 0x0000)
+                       continue;
+
+               pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN);
+
+               /* PCI spec says all values except 1..4 are reserved */
+               if ((pin < 1) || (pin > 4))
+                       continue;
+
+               line = irq[pin - 1];
+               if (!line)
+                       continue;
+
+               debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n",
+                     line, bus, device, func, 'A' + pin - 1);
+
+               x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line);
+       }
+}