karo: tx28: change FDT addr to be in low memory

[karo-tx-uboot.git] / board / cpc45 / plx9030.c

diff --git a/board/cpc45/plx9030.c b/board/cpc45/plx9030.c
index e337bd200b432123b7c14f1c4e19418ed12b8ab6..06fb8d6c9aa72f13571abc38661b692bd87b29ff 100644 (file)
--- a/board/cpc45/plx9030.c
+++ b/board/cpc45/plx9030.c
@@ -3,24 +3,7 @@
  * (C) Copyright 2002-2003
  * Josef Wagner, MicroSys GmbH, wagner@microsys.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  *   Date       Modification                                      by
  * -------      ----------------------------------------------    ---
  * 30sep02      converted from VxWorks to LINUX                   wa
@@ -54,7 +37,7 @@ registers (CS3) on CPC45.
 
 /* PLX9030 register offsets  */
 #define        P9030_LAS0RR    0x00
-#define        P9030_LAS1RR    0x04
+#define        P9030_LAS1RR    0x04
 #define        P9030_LAS2RR    0x08
 #define        P9030_LAS3RR    0x0c
 #define        P9030_EROMRR    0x10
@@ -72,8 +55,8 @@ registers (CS3) on CPC45.
 #define        P9030_CS1BASE   0x40
 #define        P9030_CS2BASE   0x44
 #define        P9030_CS3BASE   0x48
-#define        P9030_INTCSR    0x4c
-#define        P9030_CNTRL     0x50
+#define        P9030_INTCSR    0x4c
+#define        P9030_CNTRL     0x50
 #define        P9030_GPIOC     0x54
 
 /* typedefs */
@@ -137,7 +120,7 @@ void Plx9030Init (void)
        sysOutLong((membaseCsr + P9030_LAS0BA),  0x00000001);           /* enable space base */
        sysOutLong((membaseCsr + P9030_LAS0RR),  0x0FE00000);           /* 2 MByte */
        sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900);           /* 4 wait states */
-       sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001);           /* enable 2 MByte */    
+       sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001);           /* enable 2 MByte */
        /* remap CS0 (SRAM) */
        pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE);
 
@@ -145,7 +128,7 @@ void Plx9030Init (void)
        sysOutLong((membaseCsr + P9030_LAS1BA),  0x00400001);           /* enable space base */
        sysOutLong((membaseCsr + P9030_LAS1RR),  0x0FFFFF00);           /* 256 byte */
        sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900);           /* 4 wait states */
-       sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081);           /* enable 256 Byte */   
+       sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081);           /* enable 256 Byte */
        /* remap CS1 (ST16552 / CHAN A) */
        /* remap CS1 (ST16552 / CHAN A) */
        pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE);
@@ -154,7 +137,7 @@ void Plx9030Init (void)
        sysOutLong((membaseCsr + P9030_LAS2BA),  0x00800001);           /* enable space base */
        sysOutLong((membaseCsr + P9030_LAS2RR),  0x0FFFFF00);           /* 256 byte */
        sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900);           /* 4 wait states */
-       sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081);           /* enable 256 Byte */   
+       sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081);           /* enable 256 Byte */
        /* remap CS2 (ST16552 / CHAN B) */
        pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE);
 
@@ -162,7 +145,7 @@ void Plx9030Init (void)
        sysOutLong((membaseCsr + P9030_LAS3BA),  0x00C00001);           /* enable space base */
        sysOutLong((membaseCsr + P9030_LAS3RR),  0x0FFFFF00);           /* 256 byte */
        sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80);           /* 9 wait states */
-       sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081);           /* enable 256 Byte */   
+       sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081);           /* enable 256 Byte */
        /* remap CS3 (DISPLAY and BCSR) */
        pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE);
 }
@@ -171,4 +154,3 @@ void sysOutLong(ulong address, ulong value)
 {
        *(ulong*)address = cpu_to_le32(value);
 }
-