mx6: clock: use setup_gpmi_io_clk() to change nfc clk divider for CONFIG_NAND_MXS

[karo-tx-uboot.git] / board / espt / lowlevel_init.S

diff --git a/board/espt/lowlevel_init.S b/board/espt/lowlevel_init.S
index 7d5d72e123ff36e257aafa9c30c90701b4d1e707..ec9fb883f5ae00f8a7309c7876df8b89a0dbe61f 100644 (file)
--- a/board/espt/lowlevel_init.S
+++ b/board/espt/lowlevel_init.S
@@ -4,24 +4,10 @@
  *
  * board/espt/lowlevel_init.S
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <config.h>
-#include <version.h>
 #include <asm/processor.h>
 #include <asm/macro.h>
 
@@ -72,15 +58,7 @@ lowlevel_init:
        /* set DDR-SDRAM dummy read */
        write32 MMSEL_A, MMSEL_D
 
-       mov.l   MMSEL_A, r0
-       synco
-       mov.l   @r0, r1
-       synco
-
-       mov.l   CS0_A, r0
-       synco
-       mov.l   @r0, r1
-       synco
+       write32 MMSEL_A, CS0_A
 
        /* set DDR-SDRAM bus/endian etc */
        write32 MIM_U_A, MIM_U_D
@@ -214,26 +192,31 @@ PKDR_A:   .long   0xFFEF0034
 
 /* GPIO Set data */
 PADR_D:        .long   0x00000000
-PACR_D:        .long   0x00001400
+PACR_D:        .word   0x1400
+.align 2
 PBDR_D:        .long   0x00000000
-PBCR_D:        .long   0x0000555A
+PBCR_D:        .word   0x555A
+.align 2
 PCDR_D:        .long   0x00000000
-PCCR_D:        .long   0x00005555
+PCCR_D:        .word   0x5555
+.align 2
 PDDR_D:        .long   0x00000000
-PDCR_D:        .long   0x00000155
-PECR_D:        .long   0x00000000
-PFCR_D:        .long   0x00000000
-PGCR_D:        .long   0x00000000
-PHCR_D:        .long   0x00000000
-PICR_D:        .long   0x00000800
+PDCR_D:        .word   0x0155
+PECR_D:        .word   0x0000
+PFCR_D:        .word   0x0000
+PGCR_D:        .word   0x0000
+PHCR_D:        .word   0x0000
+PICR_D:        .word   0x0800
 PJDR_D:        .long   0x00000006
-PJCR_D:        .long   0x00005A57
+PJCR_D:        .word   0x5A57
+.align 2
 PKDR_D:        .long   0x00000000
-PKCR_D:        .long   0x0000FFF9
-PLCR_D:        .long   0x0000C330
-PMCR_D:        .long   0x0000FFFF
-PNCR_D:        .long   0x00000242
-POCR_D:        .long   0x00000000
+PKCR_D:        .word   0xFFF9
+.align 2
+PLCR_D:        .word   0xC330
+PMCR_D:        .word   0xFFFF
+PNCR_D:        .word   0x0242
+POCR_D:        .word   0x0000
 
 /* Pin Select */
 PSEL0_A:       .long   0xFFEF0070
@@ -241,11 +224,12 @@ PSEL1_A:  .long   0xFFEF0072
 PSEL2_A:       .long   0xFFEF0074
 PSEL3_A:       .long   0xFFEF0076
 PSEL4_A:       .long   0xFFEF0078
-PSEL0_D:       .long   0x0001
-PSEL1_D:       .long   0x2400
-PSEL2_D:       .long   0x0000
-PSEL3_D:       .long   0x2421
-PSEL4_D:       .long   0x0000
+PSEL0_D:       .word   0x0001
+PSEL1_D:       .word   0x2400
+PSEL2_D:       .word   0x0000
+PSEL3_D:       .word   0x2421
+PSEL4_D:       .word   0x0000
+.align 2
 
 MMSEL_A:       .long   0xFE600020
 BCR_A:         .long   0xFF801000