#include <common.h>
#include <config.h>
+#include <jffs2/jffs2.h>
#include <mpc8xx.h>
#include <net.h> /* for eth_init() */
#include <rtc.h>
# include <status_led.h>
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
#define ORMASK(size) ((-size) & OR_AM_MSK)
static long ram_size(ulong *, long);
/* ------------------------------------------------------------------------- */
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#if defined(CONFIG_CMD_PCMCIA)
#error "SXNI855T has no PCMCIA port"
-#endif /* CFG_CMD_PCMCIA */
+#endif
/* ------------------------------------------------------------------------- */
#define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */
#define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */
#define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */
-#define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG)) /* FPGA port */
+#define fpga (*(volatile unsigned char *)(CONFIG_SYS_FPGA_PROG)) /* FPGA port */
int board_postclk_init (void)
{
# include "fpgadata.c"
};
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
#define porta (immap->im_ioport.iop_padat)
const unsigned char* pdata;
/* write program data to FPGA at the programming address
* so extra /CS1 strobes at end of configuration don't actually
- * write to any registers.
+ * write to any registers.
*/
fpga = 0xff; /* first write is ignored */
fpga = 0xff; /* fill byte */
/* ------------------------------------------------------------------------- */
/* base address for SRAM, assume 32-bit port, valid */
-#define NVRAM_BR_VALUE (CFG_SRAM_BASE | BR_PS_32 | BR_V)
+#define NVRAM_BR_VALUE (CONFIG_SYS_SRAM_BASE | BR_PS_32 | BR_V)
/* up to 64MB - will be adjusted for actual size */
-#define NVRAM_OR_PRELIM (ORMASK(CFG_SRAM_SIZE) \
+#define NVRAM_OR_PRELIM (ORMASK(CONFIG_SYS_SRAM_SIZE) \
| OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
/*
* Miscellaneous platform dependent initializations after running in RAM.
int misc_init_r (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- char* s;
- char* e;
- int reg;
bd_t *bd = gd->bd;
+ uchar enetaddr[6];
memctl->memc_or2 = NVRAM_OR_PRELIM;
memctl->memc_br2 = NVRAM_BR_VALUE;
/* Is there any SRAM? Is it 16 or 32 bits wide? */
/* First look for 32-bit SRAM */
- bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
+ bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
if (bd->bi_sramsize == 0) {
/* no 32-bit SRAM, but there could be 16-bit SRAM since
* Try again with a 16-bit bus.
*/
memctl->memc_br2 |= BR_PS_16;
- bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
+ bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
}
if (bd->bi_sramsize == 0) {
else {
/* adjust or2 for actual size of SRAM */
memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
- bd->bi_sramstart = CFG_SRAM_BASE;
+ bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10);
}
* is present it gets a unique address, otherwise it
* shares the FEC address.
*/
- s = getenv("eth1addr");
- if (s == NULL)
- s = getenv("ethaddr");
- for (reg=0; reg<6; ++reg) {
- bd->bi_enet1addr[reg] = s ? simple_strtoul(s, &e, 16) : 0;
- if (s)
- s = (*e) ? e+1 : e;
+ if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
+ eth_getenv_enetaddr("ethaddr", enetaddr);
+ eth_setenv_enetaddr("eth1addr", enetaddr);
}
return (0);
}
+#if defined(CONFIG_CMD_NAND)
+void nand_init(void)
+{
+ unsigned long totlen = nand_probe(CONFIG_SYS_DFLASH_BASE);
+
+ printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
+
/* ------------------------------------------------------------------------- */
/*
static long ram_size(ulong *base, long maxsize)
{
volatile long *test_addr;
- volatile long *base_addr = base;
+ volatile ulong *base_addr = base;
ulong ofs; /* byte offset from base_addr */
ulong save; /* to make test non-destructive */
ulong save2; /* to make test non-destructive */
ramsize = 0; /* no RAM present, or defective */
else {
*base_addr = 0xaaaa5555;
- *(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */
+ *(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */
if (*base_addr != 0xaaaa5555)
ramsize = 0; /* no RAM present, or defective */
}
_not_used_, _not_used_, _not_used_, _not_used_,
/* single write. (offset 18 in upm RAM) */
- /* FADS had 0x1f27fc04, ...
+ /* FADS had 0x1f27fc04, ...
* but most other boards have 0x1f07fc04, which
* sets GPL0 from A11MPC to 0 1/4 clock earlier,
* like the single read.
/* ------------------------------------------------------------------------- */
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
uint size_sdram = 0;
uint size_sdram9 = 0;
* This may be too fast, but works for any memory.
* It is adjusted to 4096 cycles in 64 milliseconds if
* possible once we know what memory we have.
- *
+ *
* We have to be careful changing UPM registers after we
* ask it to run these commands.
*
* SCCR[DFBRG] 0
* PTP divide by 8
* 1 chip select
- */
+ */
memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */
memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */
return (size_sdram);
}
-
projects / karo-tx-uboot.git / blobdiff