# include <status_led.h>
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-#endif
+DECLARE_GLOBAL_DATA_PTR;
#define ORMASK(size) ((-size) & OR_AM_MSK)
/* ------------------------------------------------------------------------- */
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#if defined(CONFIG_CMD_PCMCIA)
#error "SXNI855T has no PCMCIA port"
-#endif /* CFG_CMD_PCMCIA */
+#endif
/* ------------------------------------------------------------------------- */
#define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */
#define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */
#define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */
-#define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG)) /* FPGA port */
+#define fpga (*(volatile unsigned char *)(CONFIG_SYS_FPGA_PROG)) /* FPGA port */
int board_postclk_init (void)
{
# include "fpgadata.c"
};
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
#define porta (immap->im_ioport.iop_padat)
const unsigned char* pdata;
/* ------------------------------------------------------------------------- */
/* base address for SRAM, assume 32-bit port, valid */
-#define NVRAM_BR_VALUE (CFG_SRAM_BASE | BR_PS_32 | BR_V)
+#define NVRAM_BR_VALUE (CONFIG_SYS_SRAM_BASE | BR_PS_32 | BR_V)
/* up to 64MB - will be adjusted for actual size */
-#define NVRAM_OR_PRELIM (ORMASK(CFG_SRAM_SIZE) \
+#define NVRAM_OR_PRELIM (ORMASK(CONFIG_SYS_SRAM_SIZE) \
| OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
/*
* Miscellaneous platform dependent initializations after running in RAM.
int misc_init_r (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- char* s;
- char* e;
- int reg;
bd_t *bd = gd->bd;
+ uchar enetaddr[6];
memctl->memc_or2 = NVRAM_OR_PRELIM;
memctl->memc_br2 = NVRAM_BR_VALUE;
/* Is there any SRAM? Is it 16 or 32 bits wide? */
/* First look for 32-bit SRAM */
- bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
+ bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
if (bd->bi_sramsize == 0) {
/* no 32-bit SRAM, but there could be 16-bit SRAM since
* Try again with a 16-bit bus.
*/
memctl->memc_br2 |= BR_PS_16;
- bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
+ bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
}
if (bd->bi_sramsize == 0) {
else {
/* adjust or2 for actual size of SRAM */
memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
- bd->bi_sramstart = CFG_SRAM_BASE;
+ bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10);
}
* is present it gets a unique address, otherwise it
* shares the FEC address.
*/
- s = getenv("eth1addr");
- if (s == NULL)
- s = getenv("ethaddr");
- for (reg=0; reg<6; ++reg) {
- bd->bi_enet1addr[reg] = s ? simple_strtoul(s, &e, 16) : 0;
- if (s)
- s = (*e) ? e+1 : e;
+ if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
+ eth_getenv_enetaddr("ethaddr", enetaddr);
+ eth_setenv_enetaddr("eth1addr", enetaddr);
}
return (0);
}
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
void nand_init(void)
{
- unsigned long totlen = nand_probe(CFG_NAND_BASE);
+ unsigned long totlen = nand_probe(CONFIG_SYS_DFLASH_BASE);
printf ("%4lu MB\n", totlen >> 20);
}
static long ram_size(ulong *base, long maxsize)
{
volatile long *test_addr;
- volatile long *base_addr = base;
+ volatile ulong *base_addr = base;
ulong ofs; /* byte offset from base_addr */
ulong save; /* to make test non-destructive */
ulong save2; /* to make test non-destructive */
/* ------------------------------------------------------------------------- */
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
uint size_sdram = 0;
uint size_sdram9 = 0;
return (size_sdram);
}
-
-#ifdef CFG_JFFS_CUSTOM_PART
-
-static struct part_info part;
-
-#define jffs2_block(i) \
- ((struct jffs2_unknown_node*)(CFG_JFFS2_BASE + (i) * 65536))
-
-struct part_info* jffs2_part_info(int part_num)
-{
- DECLARE_GLOBAL_DATA_PTR;
- bd_t *bd = gd->bd;
- char* s;
- int i;
- int bootnor = 0; /* assume booting from NAND flash */
-
- if (part_num != 0)
- return 0; /* only support one partition */
-
- if (part.usr_priv == (void*)1)
- return ∂ /* already have part info */
-
- memset(&part, 0, sizeof(part));
-
- if (nand_dev_desc[0].ChipID == NAND_ChipID_UNKNOWN)
- bootnor = 1;
- else if (bd->bi_flashsize < 0x800000)
- bootnor = 0;
- else for (i = 0; !bootnor && i < 4; ++i) {
- /* boot from NOR if JFFS2 info in any of
- * first 4 erase blocks
- */
-
- if (jffs2_block(i)->magic == JFFS2_MAGIC_BITMASK)
- bootnor = 1;
- }
-
- if (bootnor) {
- /* no NAND flash or boot in NOR, use NOR flash */
- part.offset = (unsigned char *)CFG_JFFS2_BASE;
- part.size = CFG_JFFS2_SIZE;
- }
- else {
- char readcmd[60];
-
- /* boot info in NAND flash, get and use copy in RAM */
-
- /* override info from environment if present */
- s = getenv("fsaddr");
- part.offset = s ? (void *)simple_strtoul(s, NULL, 16)
- : (void *)CFG_JFFS2_RAMBASE;
- s = getenv("fssize");
- part.size = s ? simple_strtoul(s, NULL, 16)
- : CFG_JFFS2_RAMSIZE;
-
- /* read from nand flash */
- sprintf(readcmd, "nand read.jffs2 %x 0 %x",
- (uint32_t)part.offset, part.size);
- run_command(readcmd, 0);
- }
-
- part.erasesize = 0; /* unused */
- part.usr_priv=(void*)1; /* ready */
-
- return ∂
-}
-#endif /* ifdef CFG_JFFS_CUSTOM_PART */
projects / karo-tx-uboot.git / blobdiff