Merge branch 'master' into next

[karo-tx-uboot.git] / board / socrates / tlb.c

diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c
index aea99ada20adeaaab9995c5b6ca2b7f4c654d1a7..4591e466b99dcebc377822c2a870387960c99165 100644 (file)
--- a/board/socrates/tlb.c
+++ b/board/socrates/tlb.c
@@ -31,26 +31,26 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
        /* TLB 0 - for temp stack in cache */
-       SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 0, BOOKE_PAGESZ_4K, 0),
-       SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 0, BOOKE_PAGESZ_4K, 0),
-       SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 0, BOOKE_PAGESZ_4K, 0),
-       SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 0, BOOKE_PAGESZ_4K, 0),
 
 
        /*
-        * TLB 0:       64M     Non-cacheable, guarded
+        * TLB 1:       64M     Non-cacheable, guarded
         * 0xfc000000   64M     FLASH
         * Out of reset this entry is only 4K.
         */
-       SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+       SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 1, BOOKE_PAGESZ_64M, 1),
 
@@ -58,7 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * TLB 2:       256M    Non-cacheable, guarded
         * 0x80000000   256M    PCI1 MEM First half
         */
-       SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -66,29 +66,41 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * TLB 3:       256M    Non-cacheable, guarded
         * 0x90000000   256M    PCI1 MEM Second half
         */
-       SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 3, BOOKE_PAGESZ_256M, 1),
 
-#if defined(CFG_FPGA_BASE)
+#if defined(CONFIG_SYS_FPGA_BASE)
        /*
         * TLB 4:       1M      Non-cacheable, guarded
         * 0xc0000000   1M      FPGA and NAND
         */
-       SET_TLB_ENTRY(1, CFG_FPGA_BASE, CFG_FPGA_BASE,
+       SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 4, BOOKE_PAGESZ_1M, 1),
 #endif
 
+       /*
+        * TLB 5:       64M     Non-cacheable, guarded
+        * 0xc8000000   16M     LIME GDC framebuffer
+        * 0xc9fc0000   256K    LIME GDC MMIO
+        * (0xcbfc0000  256K    LIME GDC MMIO)
+        * MMIO is relocatable and could be at 0xcbfc0000
+        */
+       SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 5, BOOKE_PAGESZ_64M, 1),
+
        /*
         * TLB 6:       64M     Non-cacheable, guarded
         * 0xe000_0000  1M      CCSRBAR
         * 0xe200_0000  16M     PCI1 IO
         */
-       SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+       SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 6, BOOKE_PAGESZ_64M, 1),
 
+#if !defined(CONFIG_SPD_EEPROM)
        /*
         * TLB 7+8:     512M    DDR, cache disabled (needed for memory test)
         * 0x00000000  512M     DDR System memory
@@ -96,13 +108,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * Make sure the TLB count at the top of this table is correct.
         * Likely it needs to be increased by two for these entries.
         */
-       SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 7, BOOKE_PAGESZ_256M, 1),
 
-       SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 8, BOOKE_PAGESZ_256M, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);