ppc: Refactor cache routines, so there is only one common set.

[karo-tx-uboot.git] / cpu / mpc83xx / start.S

diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index 0f27bb61f8cec196394b61ac00208dbff119b7e2..309eb30e8e97b423218d5f5f761461c5fedf1e3b 100644 (file)
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -77,19 +77,11 @@
        END_GOT
 
 /*
- * Version string - must be in data segment because MPC83xx uses the
- * first 256 bytes for the Hard Reset Configuration Word table (see
- * below).  Similarly, can't have the U-Boot Magic Number as the first
- * thing in the image - don't know how this will affect the image tools,
- * but I guess I'll find out soon.
+ * The Hard Reset Configuration Word (HRCW) table is in the first 64
+ * (0x40) bytes of flash.  It has 8 bytes, but each byte is repeated 8
+ * times so the processor can fetch it out of flash whether the flash
+ * is 8, 16, 32, or 64 bits wide (hardware trickery).
  */
-       .data
-       .globl  version_string
-version_string:
-       .ascii U_BOOT_VERSION
-       .ascii " (", __DATE__, " - ", __TIME__, ")"
-       .ascii " ", CONFIG_IDENT_STRING, "\0"
-
        .text
 #define _HRCW_TABLE_ENTRY(w)           \
        .fill   8,1,(((w)>>24)&0xff);   \
@@ -100,6 +92,18 @@ version_string:
        _HRCW_TABLE_ENTRY(CFG_HRCW_LOW)
        _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH)
 
+/*
+ * Magic number and version string - put it after the HRCW since it
+ * cannot be first in flash like it is in many other processors.
+ */
+       .long   0x27051956              /* U-Boot Magic Number */
+
+       .globl  version_string
+version_string:
+       .ascii U_BOOT_VERSION
+       .ascii " (", __DATE__, " - ", __TIME__, ")"
+       .ascii " ", CONFIG_IDENT_STRING, "\0"
+
 
 #ifndef CONFIG_DEFAULT_IMMR
 #error CONFIG_DEFAULT_IMMR must be defined
@@ -259,7 +263,7 @@ _start_of_vectors:
 /* Alignment exception. */
        . = 0x600
 Alignment:
-       EXCEPTION_PROLOG
+       EXCEPTION_PROLOG(SRR0, SRR1)
        mfspr   r4,DAR
        stw     r4,_DAR(r21)
        mfspr   r5,DSISR
@@ -278,7 +282,7 @@ Alignment:
 /* Program check exception */
        . = 0x700
 ProgramCheck:
-       EXCEPTION_PROLOG
+       EXCEPTION_PROLOG(SRR0, SRR1)
        addi    r3,r1,STACK_FRAME_OVERHEAD
        li      r20,MSR_KERNEL
        rlwimi  r20,r23,0,16,16         /* copy EE bit from saved MSR */
@@ -458,7 +462,7 @@ init_e300_core: /* time t 10 */
 
        li      r4, 0x556C
        sth     r4, SWSRR@l(r3)
-       li      r4, 0xAA39
+       li      r4, -0x55C7
        sth     r4, SWSRR@l(r3)
 #else
        /* Disable Wathcdog  */
@@ -836,40 +840,6 @@ get_pvr:
        mfspr   r3, PVR
        blr
 
-/*------------------------------------------------------------------------------- */
-/* Function:    ppcDcbf */
-/* Description:         Data Cache block flush */
-/* Input:       r3 = effective address */
-/* Output:      none. */
-/*------------------------------------------------------------------------------- */
-       .globl  ppcDcbf
-ppcDcbf:
-       dcbf    r0,r3
-       blr
-
-/*------------------------------------------------------------------------------- */
-/* Function:    ppcDcbi */
-/* Description:         Data Cache block Invalidate */
-/* Input:       r3 = effective address */
-/* Output:      none. */
-/*------------------------------------------------------------------------------- */
-       .globl  ppcDcbi
-ppcDcbi:
-       dcbi    r0,r3
-       blr
-
-/*--------------------------------------------------------------------------
- * Function:    ppcDcbz
- * Description:         Data Cache block zero.
- * Input:       r3 = effective address
- * Output:      none.
- *-------------------------------------------------------------------------- */
-
-       .globl  ppcDcbz
-ppcDcbz:
-       dcbz    r0,r3
-       blr
-
        .globl  ppcDWstore
 ppcDWstore:
        lfd     1, 0(r4)