Drop support for CONFIG_SYS_ARM_WITHOUT_RELOC

[karo-tx-uboot.git] / doc / README.fsl-ddr

diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index 9c2224fea1421793f01c9844416e919172242dfa..1657ef61702679919301536eab515d22089c9e1d 100644 (file)
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -27,43 +27,74 @@ Table of interleaving modes supported in cpu/8xxx/ddr/
  from each controller. {CS2+CS3} on each controller are only rank
  interleaved on that controller.
 
+ For memory controller interleaving, identical DIMMs are suggested. Software
+ doesn't check the size or organization of interleaved DIMMs.
+
 The ways to configure the ddr interleaving mode
 ==============================================
 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
    under "CONFIG_EXTRA_ENV_SETTINGS", like:
        #define CONFIG_EXTRA_ENV_SETTINGS                               \
-        "memctl_intlv_ctl=2\0"                                         \
+        "hwconfig=fsl_ddr:ctlr_intlv=bank"                     \
         ......
 
 2. Run u-boot "setenv" command to configure the memory interleaving mode.
    Either numerical or string value is accepted.
 
   # disable memory controller interleaving
-  setenv memctl_intlv_ctl
+  setenv hwconfig "fsl_ddr:ctlr_intlv=null"
 
   # cacheline interleaving
-  setenv memctl_intlv_ctl 0 or setenv memctl_intlv_ctl cacheline
+  setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
 
   # page interleaving
-  setenv memctl_intlv_ctl 1 or setenv memctl_intlv_ctl page
+  setenv hwconfig "fsl_ddr:ctlr_intlv=page"
 
   # bank interleaving
-  setenv memctl_intlv_ctl 2 or setenv memctl_intlv_ctl bank
+  setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
 
   # superbank
-  setenv memctl_intlv_ctl 3 or setenv memctl_intlv_ctl superbank
+  setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
 
   # disable bank (chip-select) interleaving
-  setenv ba_intlv_ctl
+  setenv hwconfig "fsl_ddr:bank_intlv=null"
 
   # bank(chip-select) interleaving cs0+cs1
-  setenv ba_intlv_ctl 0x40 or setenv ba_intlv_ctl cs0_cs1
+  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
 
   # bank(chip-select) interleaving cs2+cs3
-  setenv ba_intlv_ctl 0x20 or setenv ba_intlv_ctl cs2_cs3
+  setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
 
   # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3)  (2x2)
-  setenv ba_intlv_ctl 0x60 or setenv ba_intlv_ctl cs0_cs1_and_cs2_cs3
+  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
 
   # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
-  setenv ba_intlv_ctl 0x04 or setenv ba_intlv_ctl cs0_cs1_cs2_cs3
+  setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
+
+Memory controller address hashing
+==================================
+If the DDR controller supports address hashing, it can be enabled by hwconfig.
+
+Syntax is:
+hwconfig=fsl_ddr:addr_hash=true
+
+
+Memory testing options for mpc85xx
+==================================
+1. Memory test can be done once U-boot prompt comes up using mtest, or
+2. Memory test can be done with Power-On-Self-Test function, activated at
+   compile time.
+
+   In order to enable the POST memory test, CONFIG_POST needs to be
+   defined in board configuraiton header file. By default, POST memory test
+   performs a fast test. A slow test can be enabled by changing the flag at
+   compiling time. To test memory bigger than 2GB, 36BIT support is needed.
+   Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
+   window to physical address so that all physical memory can be tested.
+
+Combination of hwconfig
+=======================
+Hwconfig can be combined with multiple parameters, for example, on a supported
+platform
+
+hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3