(struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
- (struct socfpga_phy_mgr_cmd *)(BASE_PHY_MGR);
+ (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
- (struct socfpga_phy_mgr_cfg *)(BASE_PHY_MGR + 0x4000);
+ (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
static struct socfpga_data_mgr *data_mgr =
- (struct socfpga_data_mgr *)(BASE_DATA_MGR);
+ (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
+
+static struct socfpga_sdr_ctrl *sdr_ctrl =
+ (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
#define DELTA_D 1
-#define MGR_SELECT_MASK 0xf8000
/*
* In order to reduce ROM size, most of the selectable calibration steps are
uint32_t write_group, uint32_t use_dm,
uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
-static u32 sdr_get_addr(u32 *base)
-{
- u32 addr = (u32)base & MGR_SELECT_MASK;
-
- switch (addr) {
- case BASE_PHY_MGR:
- addr = (((u32)base >> 8) & (1 << 6)) | ((u32)base & 0x3f) |
- SDR_PHYGRP_PHYMGRGRP_ADDRESS;
- break;
- case BASE_RW_MGR:
- addr = ((u32)base & 0x1fff) | SDR_PHYGRP_RWMGRGRP_ADDRESS;
- break;
- case BASE_DATA_MGR:
- addr = ((u32)base & 0x7ff) | SDR_PHYGRP_DATAMGRGRP_ADDRESS;
- break;
- case BASE_SCC_MGR:
- addr = ((u32)base & 0xfff) | SDR_PHYGRP_SCCGRP_ADDRESS;
- break;
- case BASE_REG_FILE:
- addr = ((u32)base & 0x7ff) | SDR_PHYGRP_REGFILEGRP_ADDRESS;
- break;
- case BASE_MMR:
- addr = ((u32)base & 0xfff) | SDR_CTRLGRP_ADDRESS;
- break;
- default:
- return -1;
- }
-
- return addr;
-}
-
static void set_failing_group_stage(uint32_t group, uint32_t stage,
uint32_t substage)
{
}
}
-static void reg_file_set_group(uint32_t set_group)
+static void reg_file_set_group(u16 set_group)
{
- u32 addr = (u32)&sdr_reg_file->cur_stage;
-
- /* Read the current group and stage */
- uint32_t cur_stage_group = readl(SOCFPGA_SDR_ADDRESS + addr);
-
- /* Clear the group */
- cur_stage_group &= 0x0000FFFF;
-
- /* Set the group */
- cur_stage_group |= (set_group << 16);
-
- /* Write the data back */
- writel(cur_stage_group, SOCFPGA_SDR_ADDRESS + addr);
+ clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
}
-static void reg_file_set_stage(uint32_t set_stage)
+static void reg_file_set_stage(u8 set_stage)
{
- u32 addr = (u32)&sdr_reg_file->cur_stage;
-
- /* Read the current group and stage */
- uint32_t cur_stage_group = readl(SOCFPGA_SDR_ADDRESS + addr);
-
- /* Clear the stage and substage */
- cur_stage_group &= 0xFFFF0000;
-
- /* Set the stage */
- cur_stage_group |= (set_stage & 0x000000FF);
-
- /* Write the data back */
- writel(cur_stage_group, SOCFPGA_SDR_ADDRESS + addr);
+ clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
}
-static void reg_file_set_sub_stage(uint32_t set_sub_stage)
+static void reg_file_set_sub_stage(u8 set_sub_stage)
{
- u32 addr = (u32)&sdr_reg_file->cur_stage;
-
- /* Read the current group and stage */
- uint32_t cur_stage_group = readl(SOCFPGA_SDR_ADDRESS + addr);
-
- /* Clear the substage */
- cur_stage_group &= 0xFFFF00FF;
-
- /* Set the sub stage */
- cur_stage_group |= ((set_sub_stage << 8) & 0x0000FF00);
-
- /* Write the data back */
- writel(cur_stage_group, SOCFPGA_SDR_ADDRESS + addr);
+ set_sub_stage &= 0xff;
+ clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
}
static void initialize(void)
{
- u32 addr = sdr_get_addr(&phy_mgr_cfg->mux_sel);
-
debug("%s:%d\n", __func__, __LINE__);
/* USER calibration has control over path to memory */
/*
* 0: AFI Mux Select
* 1: DDIO Mux Select
*/
- writel(0x3, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x3, &phy_mgr_cfg->mux_sel);
/* USER memory clock is not stable we begin initialization */
- addr = sdr_get_addr(&phy_mgr_cfg->reset_mem_stbl);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &phy_mgr_cfg->reset_mem_stbl);
/* USER calibration status all set to zero */
- addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &phy_mgr_cfg->cal_status);
- addr = sdr_get_addr(&phy_mgr_cfg->cal_debug_info);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &phy_mgr_cfg->cal_debug_info);
if ((dyn_calib_steps & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) {
param->read_correct_mask_vg = ((uint32_t)1 <<
uint32_t odt_mask_0 = 0;
uint32_t odt_mask_1 = 0;
uint32_t cs_and_odt_mask;
- uint32_t addr;
if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) {
if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
(0xFF & ~(1 << rank)) |
((0xFF & odt_mask_0) << 8) |
((0xFF & odt_mask_1) << 16);
- addr = sdr_get_addr((u32 *)RW_MGR_SET_CS_AND_ODT_MASK);
- writel(cs_and_odt_mask, SOCFPGA_SDR_ADDRESS + addr);
+ writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
}
static void scc_mgr_initialize(void)
{
- u32 addr = sdr_get_addr((u32 *)SCC_MGR_HHP_RFILE);
+ u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_RFILE_OFFSET;
/*
* Clear register file for HPS
for (i = 0; i < 16; i++) {
debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
__func__, __LINE__, i);
- writel(0, SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+ writel(0, addr + (i << 2));
}
}
static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group,
uint32_t delay)
{
- u32 addr = sdr_get_addr((u32 *)SCC_MGR_DQS_IN_DELAY);
+ u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
/* Load the setting in the SCC manager */
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
+ writel(delay, addr + (read_group << 2));
}
static void scc_mgr_set_dqs_io_in_delay(uint32_t write_group,
uint32_t delay)
{
- u32 addr = sdr_get_addr((u32 *)SCC_MGR_IO_IN_DELAY);
+ u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
+ writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
}
static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
{
- u32 addr = sdr_get_addr((u32 *)SCC_MGR_DQS_EN_PHASE);
+ u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_PHASE_OFFSET;
/* Load the setting in the SCC manager */
- writel(phase, SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
+ writel(phase, addr + (read_group << 2));
}
static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
{
uint32_t r;
uint32_t update_scan_chains;
- uint32_t addr;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_set_dqs_en_phase(read_group, phase);
if (update_scan_chains) {
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(read_group, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(read_group, &sdr_scc_mgr->dqs_ena);
+ writel(0, &sdr_scc_mgr->update);
}
}
}
static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group,
uint32_t phase)
{
- u32 addr = sdr_get_addr((u32 *)SCC_MGR_DQDQS_OUT_PHASE);
+ u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQDQS_OUT_PHASE_OFFSET;
/* Load the setting in the SCC manager */
- writel(phase, SOCFPGA_SDR_ADDRESS + addr + (write_group << 2));
+ writel(phase, addr + (write_group << 2));
}
static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
{
uint32_t r;
uint32_t update_scan_chains;
- uint32_t addr;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_set_dqdqs_output_phase(write_group, phase);
if (update_scan_chains) {
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(write_group, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(write_group, &sdr_scc_mgr->dqs_ena);
+ writel(0, &sdr_scc_mgr->update);
}
}
}
static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
{
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_DQS_EN_DELAY);
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_DELAY_OFFSET;
/* Load the setting in the SCC manager */
- writel(delay + IO_DQS_EN_DELAY_OFFSET, SOCFPGA_SDR_ADDRESS + addr +
+ writel(delay + IO_DQS_EN_DELAY_OFFSET, addr +
(read_group << 2));
}
uint32_t delay)
{
uint32_t r;
- uint32_t addr;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_set_dqs_en_delay(read_group, delay);
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(read_group, SOCFPGA_SDR_ADDRESS + addr);
+ writel(read_group, &sdr_scc_mgr->dqs_ena);
/*
* In shadow register mode, the T11 settings are stored in
* registers in the core, which are updated by the DQS_ENA
* select_shadow_regs_for_update with update_scan_chains
* set to 0.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
}
/*
* In shadow register mode, the T11 settings are stored in
* select_shadow_regs_for_update with update_scan_chains
* set to 0.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
}
static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
{
uint32_t read_group;
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_OCT_OUT1_DELAY);
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_OCT_OUT1_DELAY_OFFSET;
/*
* Load the setting in the SCC manager
RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
+ writel(delay, addr + (read_group << 2));
}
static void scc_mgr_set_dq_out1_delay(uint32_t write_group,
uint32_t dq_in_group, uint32_t delay)
{
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
/* Load the setting in the SCC manager */
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (dq_in_group << 2));
+ writel(delay, addr + (dq_in_group << 2));
}
static void scc_mgr_set_dq_in_delay(uint32_t write_group,
uint32_t dq_in_group, uint32_t delay)
{
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_IN_DELAY);
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
/* Load the setting in the SCC manager */
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (dq_in_group << 2));
+ writel(delay, addr + (dq_in_group << 2));
}
static void scc_mgr_set_hhp_extras(void)
* bits: 8:8 = 1'b0 - separate OE from Output delay setting
*/
uint32_t value = (0<<8) | (0<<7) | (1<<5) | (1<<2) | (1<<1) | (1<<0);
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_HHP_GLOBALS);
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_GLOBALS_OFFSET;
- writel(value, SOCFPGA_SDR_ADDRESS + addr + SCC_MGR_HHP_EXTRAS_OFFSET);
+ writel(value, addr + SCC_MGR_HHP_EXTRAS_OFFSET);
}
static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
uint32_t delay)
{
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
/* Load the setting in the SCC manager */
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
+ writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
}
static void scc_mgr_set_dm_out1_delay(uint32_t write_group,
uint32_t dm, uint32_t delay)
{
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
/* Load the setting in the SCC manager */
- writel(delay, SOCFPGA_SDR_ADDRESS + addr +
+ writel(delay, addr +
((RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm) << 2));
}
static void scc_mgr_zero_all(void)
{
uint32_t i, r;
- uint32_t addr;
/*
* USER Zero all DQS config settings, across all groups and all
}
/* multicast to all DQS group enables */
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, &sdr_scc_mgr->dqs_ena);
+ writel(0, &sdr_scc_mgr->update);
}
static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
{
- uint32_t addr;
/* mode = 0 : Do NOT bypass - Half Rate Mode */
/* mode = 1 : Bypass - Full Rate Mode */
__func__, __LINE__);
}
/* multicast to all DQ enables */
- addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, &sdr_scc_mgr->dq_ena);
+ writel(0xff, &sdr_scc_mgr->dm_ena);
/* update current DQS IO enable */
- addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->dqs_io_ena);
/* update the DQS logic */
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(write_group, SOCFPGA_SDR_ADDRESS + addr);
+ writel(write_group, &sdr_scc_mgr->dqs_ena);
/* hit update */
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
}
static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
int32_t out_only)
{
uint32_t i, r;
- uint32_t addr;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
NUM_RANKS_PER_SHADOW_REG) {
}
/* multicast to all DQ enables */
- addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, &sdr_scc_mgr->dq_ena);
/* Zero all DM config settings */
for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
}
/* multicast to all DM enables */
- addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, &sdr_scc_mgr->dm_ena);
/* zero all DQS io settings */
if (!out_only)
scc_mgr_load_dqs_for_write_group(write_group);
/* multicast to all DQS IO enables (only 1) */
- addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->dqs_io_ena);
/* hit update to zero everything */
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
}
}
/* load up dqs config settings */
static void scc_mgr_load_dqs(uint32_t dqs)
{
- uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;
-
- writel(dqs, SOCFPGA_SDR_ADDRESS + addr);
+ writel(dqs, &sdr_scc_mgr->dqs_ena);
}
static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
- writel(read_group, SOCFPGA_SDR_ADDRESS + addr);
+ writel(read_group, addr);
}
/* load up dqs io config settings */
static void scc_mgr_load_dqs_io(void)
{
- uint32_t addr = (u32)&sdr_scc_mgr->dqs_io_ena;
-
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->dqs_io_ena);
}
/* load up dq config settings */
static void scc_mgr_load_dq(uint32_t dq_in_group)
{
- uint32_t addr = (u32)&sdr_scc_mgr->dq_ena;
-
- writel(dq_in_group, SOCFPGA_SDR_ADDRESS + addr);
+ writel(dq_in_group, &sdr_scc_mgr->dq_ena);
}
/* load up dm config settings */
static void scc_mgr_load_dm(uint32_t dm)
{
- uint32_t addr = (u32)&sdr_scc_mgr->dm_ena;
-
- writel(dm, SOCFPGA_SDR_ADDRESS + addr);
+ writel(dm, &sdr_scc_mgr->dm_ena);
}
/*
uint32_t write_group, uint32_t group_bgn, uint32_t delay)
{
uint32_t r;
- uint32_t addr = (u32)&sdr_scc_mgr->update;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_apply_group_all_out_delay_add(write_group,
group_bgn, delay);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
}
}
/* could be applied to other protocols if we wanted to */
static void set_jump_as_return(void)
{
- uint32_t addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
-
/*
* to save space, we replace return with jump to special shared
* RETURN instruction so we set the counter to large value so that
* we always jump
*/
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_RETURN, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
+ writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
}
/*
uint8_t inner = 0;
uint8_t outer = 0;
uint16_t c_loop = 0;
- uint32_t addr;
debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
* overhead
*/
if (afi_clocks <= 0x100) {
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), SOCFPGA_SDR_ADDRESS + addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
+ &sdr_rw_load_mgr_regs->load_cntr1);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_IDLE_LOOP1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_IDLE_LOOP1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} else {
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), SOCFPGA_SDR_ADDRESS + addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
+ &sdr_rw_load_mgr_regs->load_cntr0);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer), SOCFPGA_SDR_ADDRESS + addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
+ &sdr_rw_load_mgr_regs->load_cntr1);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
/* hack to get around compiler not being smart enough */
if (afi_clocks <= 0x10000) {
/* only need to run once */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} else {
do {
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP2,
+ SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} while (c_loop-- != 0);
}
}
static void rw_mgr_mem_initialize(void)
{
uint32_t r;
- uint32_t addr;
+ uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET;
debug("%s:%d\n", __func__, __LINE__);
/* The reset / cke part of initialization is broadcasted to all ranks */
- addr = sdr_get_addr((u32 *)RW_MGR_SET_CS_AND_ODT_MASK);
- writel(RW_MGR_RANK_ALL, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
/*
* Here's how you load register for a loop
*/
/* Load counters */
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
+ &sdr_rw_load_mgr_regs->load_cntr0);
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
+ &sdr_rw_load_mgr_regs->load_cntr1);
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
+ &sdr_rw_load_mgr_regs->load_cntr2);
/* Load jump address */
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_INIT_RESET_0_CKE_0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(RW_MGR_INIT_RESET_0_CKE_0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ writel(RW_MGR_INIT_RESET_0_CKE_0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
/* Execute count instruction */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_INIT_RESET_0_CKE_0, grpaddr);
/* indicate that memory is stable */
- addr = sdr_get_addr(&phy_mgr_cfg->reset_mem_stbl);
- writel(1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(1, &phy_mgr_cfg->reset_mem_stbl);
/*
* transition the RESET to high
*/
/* Load counters */
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
+ &sdr_rw_load_mgr_regs->load_cntr0);
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
+ &sdr_rw_load_mgr_regs->load_cntr1);
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
+ &sdr_rw_load_mgr_regs->load_cntr2);
/* Load jump address */
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_INIT_RESET_1_CKE_0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(RW_MGR_INIT_RESET_1_CKE_0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ writel(RW_MGR_INIT_RESET_1_CKE_0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_INIT_RESET_1_CKE_0, grpaddr);
/* bring up clock enable */
*/
if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
set_jump_as_return();
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_MRS2_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS2_MIRR, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS3_MIRR, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS1_MIRR, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS0_DLL_RESET_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS0_DLL_RESET_MIRR, grpaddr);
} else {
set_jump_as_return();
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_MRS2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS2, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS3, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS1, grpaddr);
set_jump_as_return();
- writel(RW_MGR_MRS0_DLL_RESET, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS0_DLL_RESET, grpaddr);
}
set_jump_as_return();
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_ZQCL, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_ZQCL, grpaddr);
/* tZQinit = tDLLK = 512 ck cycles */
delay_for_n_mem_clocks(512);
static void rw_mgr_mem_handoff(void)
{
uint32_t r;
- uint32_t addr;
+ uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET;
debug("%s:%d\n", __func__, __LINE__);
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
/* precharge all banks ... */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_PRECHARGE_ALL, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_PRECHARGE_ALL, grpaddr);
/* load up MR settings specified by user */
* Use Mirror-ed commands for odd ranks if address
* mirrorring is on
*/
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
set_jump_as_return();
- writel(RW_MGR_MRS2_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS2_MIRR, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS3_MIRR, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS1_MIRR, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS0_USER_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS0_USER_MIRR, grpaddr);
} else {
set_jump_as_return();
- writel(RW_MGR_MRS2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS2, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS3, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS1, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS0_USER, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS0_USER, grpaddr);
}
/*
* USER need to wait tMOD (12CK or 15ns) time before issuing
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts of read commands */
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_GUARANTEED_READ, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
+ writel(RW_MGR_GUARANTEED_READ,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_GUARANTEED_READ_CONT, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
+ writel(RW_MGR_GUARANTEED_READ_CONT,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
tmp_bit_chk = 0;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr((u32 *)RW_MGR_RESET_READ_DATAPATH);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
+ writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RESET_READ_DATAPATH_OFFSET);
tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
/ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_GUARANTEED_READ, SOCFPGA_SDR_ADDRESS + addr +
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ writel(RW_MGR_GUARANTEED_READ, addr +
((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
vg) << 2));
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
- base_rw_mgr = readl(SOCFPGA_SDR_ADDRESS + addr);
+ base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
if (vg == 0)
*bit_chk &= tmp_bit_chk;
}
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_CLEAR_DQS_ENABLE, SOCFPGA_SDR_ADDRESS + addr + (group << 2));
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
uint32_t all_ranks)
{
uint32_t r;
- uint32_t addr;
uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts */
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0x04, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;
- writel(0x04, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT3, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_GUARANTEED_WRITE, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
}
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
/* set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x10, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_READ_B2B_WAIT1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_READ_B2B_WAIT1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0x10, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_READ_B2B_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
+ writel(RW_MGR_READ_B2B_WAIT2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
if (quick_read_mode)
- writel(0x1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
/* need at least two (1+1) reads to capture failures */
else if (all_groups)
- writel(0x06, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
else
- writel(0x32, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_READ_B2B, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;
+ writel(RW_MGR_READ_B2B,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
if (all_groups)
writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
- SOCFPGA_SDR_ADDRESS + addr);
+ &sdr_rw_load_mgr_regs->load_cntr3);
else
- writel(0x0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_READ_B2B, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_READ_B2B,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
tmp_bit_chk = 0;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr((u32 *)RW_MGR_RESET_READ_DATAPATH);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
+ writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RESET_READ_DATAPATH_OFFSET);
tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
/ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
- addr = sdr_get_addr((u32 *)(all_groups ? RW_MGR_RUN_ALL_GROUPS :
- RW_MGR_RUN_SINGLE_GROUP));
- writel(RW_MGR_READ_B2B, SOCFPGA_SDR_ADDRESS + addr +
+ if (all_groups)
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
+ else
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+
+ writel(RW_MGR_READ_B2B, addr +
((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
vg) << 2));
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
- base_rw_mgr = readl(SOCFPGA_SDR_ADDRESS + addr);
+ base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
if (vg == 0)
*bit_chk &= tmp_bit_chk;
}
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_CLEAR_DQS_ENABLE, SOCFPGA_SDR_ADDRESS + addr + (group << 2));
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
if (all_correct) {
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
{
- uint32_t addr = sdr_get_addr(&phy_mgr_cmd->inc_vfifo_hard_phy);
-
- writel(grp, SOCFPGA_SDR_ADDRESS + addr);
+ writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
(*v)++;
}
uint32_t dtaps_per_ptap;
uint32_t work_bgn, work_mid, work_end;
uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
- uint32_t addr;
debug("%s:%d %u\n", __func__, __LINE__, grp);
if (found_passing_read && found_failing_read)
dtaps_per_ptap = d - initial_failing_dtap;
- addr = (u32)&sdr_reg_file->dtaps_per_ptap;
- writel(dtaps_per_ptap, SOCFPGA_SDR_ADDRESS + addr);
+ writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
- %u = %u", __func__, __LINE__, d,
initial_failing_dtap, dtaps_per_ptap);
uint32_t p;
uint32_t d;
uint32_t r;
- uint32_t addr;
const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
(RW_MGR_MEM_DQ_PER_READ_DQS-1);
scc_mgr_set_dq_in_delay(write_group, p, d);
scc_mgr_load_dq(p);
}
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
}
found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
scc_mgr_set_dq_in_delay(write_group, p, 0);
scc_mgr_load_dq(p);
}
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
}
return found;
debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
- addr = sdr_get_addr((u32 *)SCC_MGR_DQS_IN_DELAY);
- start_dqs = readl(SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
+ start_dqs = readl(addr + (read_group << 2));
if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
- start_dqs_en = readl(SOCFPGA_SDR_ADDRESS + addr + ((read_group << 2)
+ start_dqs_en = readl(addr + ((read_group << 2)
- IO_DQS_EN_DELAY_OFFSET));
/* set the left and right edge of each bit to an illegal value */
right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
}
- addr = (u32)&sdr_scc_mgr->update;
/* Search for the left edge of the window for each bit */
for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
break;
}
- addr = (u32)&sdr_scc_mgr->update;
/* Search for the right edge of the window for each bit */
for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
}
scc_mgr_load_dqs(read_group);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
}
/* Check that all bits have a window */
- addr = (u32)&sdr_scc_mgr->update;
for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
%d right_edge[%u]: %d", __func__, __LINE__,
start_dqs_en);
}
scc_mgr_load_dqs(read_group);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
find edge [%u]: %d %d", __func__, __LINE__,
dqs_margin = IO_IO_IN_DELAY_MAX + 1;
dq_margin = IO_IO_IN_DELAY_MAX + 1;
- addr = sdr_get_addr((u32 *)SCC_MGR_IO_IN_DELAY);
/* add delay to bring centre of all DQ windows to the same "level" */
for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
/* Use values before divide by 2 to reduce round off error */
debug_cond(DLEVEL == 2, "vfifo_center: before: \
shift_dq[%u]=%d\n", i, shift_dq);
- temp_dq_in_delay1 = readl(SOCFPGA_SDR_ADDRESS + addr + (p << 2));
- temp_dq_in_delay2 = readl(SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
+ temp_dq_in_delay1 = readl(addr + (p << 2));
+ temp_dq_in_delay2 = readl(addr + (i << 2));
if (shift_dq + (int32_t)temp_dq_in_delay1 >
(int32_t)IO_IO_IN_DELAY_MAX) {
* Do not remove this line as it makes sure all of our decisions
* have been applied. Apply the update bit.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
return (dq_margin >= 0) && (dqs_margin >= 0);
}
{
uint32_t found_one;
uint32_t bit_chk;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
rw_mgr_mem_calibrate_read_load_patterns(0, 1);
found_one = 0;
- addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
do {
- writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
__func__, __LINE__, gbl->curr_read_lat);
/* reset the fifos to get pointers to known state */
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
if (found_one) {
/* add a fudge factor to the read latency that was determined */
gbl->curr_read_lat += 2;
- addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
- writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
read_lat=%u\n", __func__, __LINE__,
gbl->curr_read_lat);
* instruction that sends out the data. We set the counter to a
* large number so that the jump is always taken.
*/
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0xFF, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
/* CNTR 3 - Not used */
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
- SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
- SOCFPGA_SDR_ADDRESS + addr);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
} else if (rw_wl_nop_cycles == 0) {
/*
* to the DQS enable instruction. We set the counter to a large
* number so that the jump is always taken.
*/
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0xFF, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
/* CNTR 3 - Not used */
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
- SOCFPGA_SDR_ADDRESS + addr);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
}
} else {
/*
* and NOT take the jump. So we set the counter to 0. The jump
* address doesn't count.
*/
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0x0, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(0x0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
+ writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
/*
* CNTR 3 - Set the nop counter to the number of cycles we
* need to loop for, minus 1.
*/
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;
- writel(rw_wl_nop_cycles - 1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
}
- addr = sdr_get_addr((u32 *)RW_MGR_RESET_READ_DATAPATH);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RESET_READ_DATAPATH_OFFSET);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
if (quick_write_mode)
- writel(0x08, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
else
- writel(0x40, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(mcc_instruction, SOCFPGA_SDR_ADDRESS + addr);
+ writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
/*
* CNTR 1 - This is used to ensure enough time elapses
* for read data to come back.
*/
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x30, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
if (test_dm) {
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
} else {
- writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
}
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(mcc_instruction, SOCFPGA_SDR_ADDRESS + addr + (group << 2));
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ writel(mcc_instruction, addr + (group << 2));
}
/* Test writes, can check for a single bit pass or multiple bit pass */
uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
uint32_t *bit_chk, uint32_t all_ranks)
{
- uint32_t addr;
uint32_t r;
uint32_t correct_mask_vg;
uint32_t tmp_bit_chk;
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
tmp_bit_chk = 0;
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
tmp_bit_chk = tmp_bit_chk <<
(RW_MGR_MEM_DQ_PER_WRITE_DQS /
RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
use_dm);
- base_rw_mgr = readl(SOCFPGA_SDR_ADDRESS + addr_rw_mgr);
+ base_rw_mgr = readl(addr_rw_mgr);
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
if (vg == 0)
break;
dm_margin = 0;
- addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
- start_dqs = readl(SOCFPGA_SDR_ADDRESS + addr +
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
+ start_dqs = readl(addr +
(RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
/* per-bit deskew */
}
/* Search for the left edge of the window for each bit */
- addr = (u32)&sdr_scc_mgr->update;
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, d);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
}
/* Search for the right edge of the window for each bit */
- addr = (u32)&sdr_scc_mgr->update;
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
d + start_dqs);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
/* add delay to bring centre of all DQ windows to the same "level" */
- addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
/* Use values before divide by 2 to reduce round off error */
shift_dq = (left_edge[i] - right_edge[i] -
debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
[%u]=%d\n", __func__, __LINE__, i, shift_dq);
- temp_dq_out1_delay = readl(SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
+ temp_dq_out1_delay = readl(addr + (i << 2));
if (shift_dq + (int32_t)temp_dq_out1_delay >
(int32_t)IO_IO_OUT1_DELAY_MAX) {
shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
/* Move DQS */
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
/* Centre DM */
debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
int32_t win_best = 0;
/* Search for the/part of the window with DM shift */
- addr = (u32)&sdr_scc_mgr->update;
for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
scc_mgr_apply_group_dm_out1_delay(write_group, d);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
PASS_ALL_BITS, &bit_chk,
}
/* Search for the/part of the window with DQS shifts */
- addr = (u32)&sdr_scc_mgr->update;
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
/*
* Note: This only shifts DQS, so are we limiting ourselve to
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
d + new_dqs);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
PASS_ALL_BITS, &bit_chk,
0)) {
dm_margin = left_edge[0] - mid;
scc_mgr_apply_group_dm_out1_delay(write_group, mid);
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
dm_margin=%d\n", __func__, __LINE__, left_edge[0],
* Do not remove this line as it makes sure all of our
* decisions have been applied.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
}
static void mem_precharge_and_activate(void)
{
uint32_t r;
- uint32_t addr;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
if (param->skip_ranks[r]) {
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
/* precharge all banks ... */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_PRECHARGE_ALL, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(0x0F, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
+ writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x0F, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
+ writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
/* activate rows */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
- writel(RW_MGR_ACTIVATE_0_AND_1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
}
}
uint32_t rlat, wlat;
uint32_t rw_wl_nop_cycles;
uint32_t max_latency;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
/* read in write and read latency */
- addr = sdr_get_addr(&data_mgr->t_wl_add);
- wlat = readl(SOCFPGA_SDR_ADDRESS + addr);
+ wlat = readl(&data_mgr->t_wl_add);
+ wlat += readl(&data_mgr->mem_t_add);
- addr = sdr_get_addr(&data_mgr->mem_t_add);
- wlat += readl(SOCFPGA_SDR_ADDRESS + addr);
/* WL for hard phy does not include additive latency */
/*
*/
wlat = wlat + 1;
- addr = sdr_get_addr(&data_mgr->t_rl_add);
- rlat = readl(SOCFPGA_SDR_ADDRESS + addr);
+ rlat = readl(&data_mgr->t_rl_add);
rw_wl_nop_cycles = wlat - 2;
gbl->rw_wl_nop_cycles = rw_wl_nop_cycles;
if (gbl->curr_read_lat > max_latency)
gbl->curr_read_lat = max_latency;
- addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
- writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
/* advertise write latency */
gbl->curr_write_lat = wlat;
- addr = sdr_get_addr(&phy_mgr_cfg->afi_wlat);
- writel(wlat - 2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(wlat - 2, &phy_mgr_cfg->afi_wlat);
/* initialize bit slips */
mem_precharge_and_activate();
{
uint32_t vfifo_offset;
uint32_t i, j, r;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
/* Need to update every shadow register set used by the interface */
scc_mgr_set_dqdqs_output_phase(i, (1.25 *
IO_DLL_CHAIN_LENGTH - 2));
}
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, &sdr_scc_mgr->dqs_ena);
+ writel(0xff, &sdr_scc_mgr->dqs_io_ena);
- addr = sdr_get_addr((u32 *)SCC_MGR_GROUP_COUNTER);
for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
- writel(i, SOCFPGA_SDR_ADDRESS + addr);
+ writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_GROUP_COUNTER_OFFSET);
}
- addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, &sdr_scc_mgr->dq_ena);
+ writel(0xff, &sdr_scc_mgr->dm_ena);
+ writel(0, &sdr_scc_mgr->update);
}
/* Compensate for simulation model behaviour */
scc_mgr_set_dqs_bus_in_delay(i, 10);
scc_mgr_load_dqs(i);
}
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* ArriaV has hard FIFOs that can only be initialized by incrementing
* in sequencer.
*/
vfifo_offset = CALIB_VFIFO_OFFSET;
- addr = sdr_get_addr(&phy_mgr_cmd->inc_vfifo_hard_phy);
for (j = 0; j < vfifo_offset; j++) {
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
}
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
/*
* For ACV with hard lfifo, we get the skip-cal setting from
* generation-time constant.
*/
gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
- addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
- writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
}
/* Memory calibration entry point */
uint32_t failing_groups = 0;
uint32_t group_failed = 0;
uint32_t sr_failed = 0;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
/* Initialize the data settings */
mem_config();
uint32_t bypass_mode = 0x1;
- addr = sdr_get_addr((u32 *)SCC_MGR_GROUP_COUNTER);
for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
- writel(i, SOCFPGA_SDR_ADDRESS + addr);
+ writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_GROUP_COUNTER_OFFSET);
scc_set_bypass_mode(i, bypass_mode);
}
if (current_run == 0)
continue;
- addr = sdr_get_addr((u32 *)SCC_MGR_GROUP_COUNTER);
- writel(write_group, SOCFPGA_SDR_ADDRESS + addr);
+ writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_GROUP_COUNTER_OFFSET);
scc_mgr_zero_group(write_group, write_test_bgn,
0);
* Do not remove this line as it makes sure all of our decisions
* have been applied.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &sdr_scc_mgr->update);
return 1;
}
{
uint32_t pass;
uint32_t debug_info;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
/* Reset pass/fail status shown on afi_cal_success/fail */
- addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
- writel(PHY_MGR_CAL_RESET, SOCFPGA_SDR_ADDRESS + addr);
+ writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
- addr = sdr_get_addr((u32 *)BASE_MMR);
/* stop tracking manger */
- uint32_t ctrlcfg = readl(SOCFPGA_SDR_ADDRESS + addr);
+ uint32_t ctrlcfg = readl(&sdr_ctrl->ctrl_cfg);
- addr = sdr_get_addr((u32 *)BASE_MMR);
- writel(ctrlcfg & 0xFFBFFFFF, SOCFPGA_SDR_ADDRESS + addr);
+ writel(ctrlcfg & 0xFFBFFFFF, &sdr_ctrl->ctrl_cfg);
initialize();
rw_mgr_mem_initialize();
pass = mem_calibrate();
mem_precharge_and_activate();
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
/*
* Handoff:
* 0: AFI Mux Select
* 1: DDIO Mux Select
*/
- addr = sdr_get_addr(&phy_mgr_cfg->mux_sel);
- writel(0x2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x2, &phy_mgr_cfg->mux_sel);
}
- addr = sdr_get_addr((u32 *)BASE_MMR);
- writel(ctrlcfg, SOCFPGA_SDR_ADDRESS + addr);
+ writel(ctrlcfg, &sdr_ctrl->ctrl_cfg);
if (pass) {
printf("%s: CALIBRATION PASSED\n", __FILE__);
/* Update the FOM in the register file */
debug_info = gbl->fom_in;
debug_info |= gbl->fom_out << 8;
- addr = (u32)&sdr_reg_file->fom;
- writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
+ writel(debug_info, &sdr_reg_file->fom);
- addr = sdr_get_addr(&phy_mgr_cfg->cal_debug_info);
- writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
- writel(PHY_MGR_CAL_SUCCESS, SOCFPGA_SDR_ADDRESS + addr);
+ writel(debug_info, &phy_mgr_cfg->cal_debug_info);
+ writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
} else {
printf("%s: CALIBRATION FAILED\n", __FILE__);
debug_info |= gbl->error_substage << 8;
debug_info |= gbl->error_group << 16;
- addr = (u32)&sdr_reg_file->failing_stage;
- writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&phy_mgr_cfg->cal_debug_info);
- writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
- writel(PHY_MGR_CAL_FAIL, SOCFPGA_SDR_ADDRESS + addr);
+ writel(debug_info, &sdr_reg_file->failing_stage);
+ writel(debug_info, &phy_mgr_cfg->cal_debug_info);
+ writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
/* Update the failing group/stage in the register file */
debug_info = gbl->error_stage;
debug_info |= gbl->error_substage << 8;
debug_info |= gbl->error_group << 16;
- addr = (u32)&sdr_reg_file->failing_stage;
- writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
+ writel(debug_info, &sdr_reg_file->failing_stage);
}
return pass;
}
+/**
+ * hc_initialize_rom_data() - Initialize ROM data
+ *
+ * Initialize ROM data.
+ */
static void hc_initialize_rom_data(void)
{
- uint32_t i;
- uint32_t addr;
+ u32 i, addr;
- addr = sdr_get_addr((u32 *)(RW_MGR_INST_ROM_WRITE));
- for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++) {
- uint32_t data = inst_rom_init[i];
- writel(data, SOCFPGA_SDR_ADDRESS + addr + (i << 2));
- }
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
+ for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
+ writel(inst_rom_init[i], addr + (i << 2));
- addr = sdr_get_addr((u32 *)(RW_MGR_AC_ROM_WRITE));
- for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++) {
- uint32_t data = ac_rom_init[i];
- writel(data, SOCFPGA_SDR_ADDRESS + addr + (i << 2));
- }
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
+ for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
+ writel(ac_rom_init[i], addr + (i << 2));
}
+/**
+ * initialize_reg_file() - Initialize SDR register file
+ *
+ * Initialize SDR register file.
+ */
static void initialize_reg_file(void)
{
- uint32_t addr;
-
/* Initialize the register file with the correct data */
- addr = (u32)&sdr_reg_file->signature;
- writel(REG_FILE_INIT_SEQ_SIGNATURE, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->debug_data_addr;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->cur_stage;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->fom;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->failing_stage;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->debug1;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->debug2;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
+ writel(0, &sdr_reg_file->debug_data_addr);
+ writel(0, &sdr_reg_file->cur_stage);
+ writel(0, &sdr_reg_file->fom);
+ writel(0, &sdr_reg_file->failing_stage);
+ writel(0, &sdr_reg_file->debug1);
+ writel(0, &sdr_reg_file->debug2);
}
+/**
+ * initialize_hps_phy() - Initialize HPS PHY
+ *
+ * Initialize HPS PHY.
+ */
static void initialize_hps_phy(void)
{
uint32_t reg;
- uint32_t addr;
/*
* Tracking also gets configured here because it's in the
* same register.
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
trk_sample_count);
- addr = sdr_get_addr((u32 *)BASE_MMR);
- writel(reg, SOCFPGA_SDR_ADDRESS + addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET);
+ writel(reg, &sdr_ctrl->phy_ctrl0);
reg = 0;
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
trk_long_idle_sample_count);
- writel(reg, SOCFPGA_SDR_ADDRESS + addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET);
+ writel(reg, &sdr_ctrl->phy_ctrl1);
reg = 0;
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
trk_long_idle_sample_count >>
SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
- writel(reg, SOCFPGA_SDR_ADDRESS + addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET);
+ writel(reg, &sdr_ctrl->phy_ctrl2);
}
static void initialize_tracking(void)
uint32_t trk_sample_count = 7500;
uint32_t dtaps_per_ptap;
uint32_t tmp_delay;
- uint32_t addr;
/*
* compute usable version of value in case we skip full
concatenated_refresh = concatenated_refresh ^ 1000; /* trefi */
/* Initialize the register file with the correct data */
- addr = (u32)&sdr_reg_file->dtaps_per_ptap;
- writel(dtaps_per_ptap, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->trk_sample_count;
- writel(trk_sample_count, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->trk_longidle;
- writel(concatenated_longidle, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->delays;
- writel(concatenated_delays, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->trk_rw_mgr_addr;
- writel(concatenated_rw_addr, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->trk_read_dqs_width;
- writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, SOCFPGA_SDR_ADDRESS + addr);
-
- addr = (u32)&sdr_reg_file->trk_rfsh;
- writel(concatenated_refresh, SOCFPGA_SDR_ADDRESS + addr);
+ writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
+ writel(trk_sample_count, &sdr_reg_file->trk_sample_count);
+ writel(concatenated_longidle, &sdr_reg_file->trk_longidle);
+ writel(concatenated_delays, &sdr_reg_file->delays);
+ writel(concatenated_rw_addr, &sdr_reg_file->trk_rw_mgr_addr);
+ writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, &sdr_reg_file->trk_read_dqs_width);
+ writel(concatenated_refresh, &sdr_reg_file->trk_rfsh);
}
int sdram_calibration_full(void)
projects / karo-tx-uboot.git / blobdiff