drm/nouveau/disp/g94-: port OR DP training pattern control to nvkm_ior

[karo-tx-linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / disp / sorgm200.c

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c
index 81b788fa61be43fcf67aa991b2821141e3c35cf4..2d32bcc8aa8a774598302bac226da0bfa08a6a35 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c
@@ -21,10 +21,8 @@
  *
  * Authors: Ben Skeggs
  */
+#include "ior.h"
 #include "nv50.h"
-#include "outpdp.h"
-
-#include <subdev/timer.h>
 
 static inline u32
 gm200_sor_soff(struct nvkm_output_dp *outp)
@@ -38,42 +36,10 @@ gm200_sor_loff(struct nvkm_output_dp *outp)
        return gm200_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
 }
 
-void
-gm200_sor_magic(struct nvkm_output *outp)
-{
-       struct nvkm_device *device = outp->disp->engine.subdev.device;
-       const u32 soff = outp->or * 0x100;
-       const u32 data = outp->or + 1;
-       if (outp->info.sorconf.link & 1)
-               nvkm_mask(device, 0x612308 + soff, 0x0000001f, 0x00000000 | data);
-       if (outp->info.sorconf.link & 2)
-               nvkm_mask(device, 0x612388 + soff, 0x0000001f, 0x00000010 | data);
-}
-
 static inline u32
 gm200_sor_dp_lane_map(struct nvkm_device *device, u8 lane)
 {
-       return lane * 0x08;
-}
-
-static int
-gm200_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
-{
-       struct nvkm_device *device = outp->base.disp->engine.subdev.device;
-       const u32 soff = gm200_sor_soff(outp);
-       const u32 loff = gm200_sor_loff(outp);
-       u32 mask = 0, i;
-
-       for (i = 0; i < nr; i++)
-               mask |= 1 << (gm200_sor_dp_lane_map(device, i) >> 3);
-
-       nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask);
-       nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000);
-       nvkm_msec(device, 2000,
-               if (!(nvkm_rd32(device, 0x61c034 + soff) & 0x80000000))
-                       break;
-       );
-       return 0;
+       return nvkm_ior_find(device->disp, SOR, -1)->func->dp.lanes[lane] * 8;
 }
 
 static int
@@ -116,9 +82,6 @@ gm200_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
 
 static const struct nvkm_output_dp_func
 gm200_sor_dp_func = {
-       .pattern = gm107_sor_dp_pattern,
-       .lnk_pwr = gm200_sor_dp_lnk_pwr,
-       .lnk_ctl = gf119_sor_dp_lnk_ctl,
        .drv_ctl = gm200_sor_dp_drv_ctl,
        .vcpi = gf119_sor_dp_vcpi,
 };
@@ -129,3 +92,36 @@ gm200_sor_dp_new(struct nvkm_disp *disp, int index, struct dcb_output *dcbE,
 {
        return nvkm_output_dp_new_(&gm200_sor_dp_func, disp, index, dcbE, poutp);
 }
+
+void
+gm200_sor_magic(struct nvkm_output *outp)
+{
+       struct nvkm_device *device = outp->disp->engine.subdev.device;
+       const u32 soff = outp->or * 0x100;
+       const u32 data = outp->or + 1;
+       if (outp->info.sorconf.link & 1)
+               nvkm_mask(device, 0x612308 + soff, 0x0000001f, 0x00000000 | data);
+       if (outp->info.sorconf.link & 2)
+               nvkm_mask(device, 0x612388 + soff, 0x0000001f, 0x00000010 | data);
+}
+
+static const struct nvkm_ior_func
+gm200_sor = {
+       .state = gf119_sor_state,
+       .power = nv50_sor_power,
+       .hdmi = {
+               .ctrl = gk104_hdmi_ctrl,
+       },
+       .dp = {
+               .lanes = { 0, 1, 2, 3 },
+               .links = gf119_sor_dp_links,
+               .power = g94_sor_dp_power,
+               .pattern = gm107_sor_dp_pattern,
+       },
+};
+
+int
+gm200_sor_new(struct nvkm_disp *disp, int id)
+{
+       return nvkm_ior_new_(&gm200_sor, disp, SOR, id);
+}