sh_eth: remove 'register_type' field from 'struct sh_eth_plat_data'

[karo-tx-linux.git] / drivers / net / ethernet / renesas / sh_eth.h

diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
index 62689a5823be3461285a17a2257b055bc250336f..a0db02c63b1157930ca0fca070dd733aa39b7c54 100644 (file)
--- a/drivers/net/ethernet/renesas/sh_eth.h
+++ b/drivers/net/ethernet/renesas/sh_eth.h
@@ -60,6 +60,7 @@ enum {
        EDOCR,
        TFUCR,
        RFOCR,
+       RMIIMODE,
        FCFTR,
        RPADIR,
        TRIMD,
@@ -156,6 +157,13 @@ enum {
        SH_ETH_MAX_REGISTER_OFFSET,
 };
 
+enum {
+       SH_ETH_REG_GIGABIT,
+       SH_ETH_REG_FAST_RCAR,
+       SH_ETH_REG_FAST_SH4,
+       SH_ETH_REG_FAST_SH3_SH2
+};
+
 /* Driver's parameters */
 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 #define SH4_SKB_RX_ALIGN       32
@@ -166,19 +174,16 @@ enum {
 /*
  * Register's bits
  */
-#if defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) ||\
-    defined(CONFIG_ARCH_R8A7740)
-/* EDSR */
+/* EDSR : sh7734, sh7757, sh7763, and r8a7740 only */
 enum EDSR_BIT {
        EDSR_ENT = 0x01, EDSR_ENR = 0x02,
 };
 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
 
-/* GECMR */
+/* GECMR : sh7734, sh7763 and r8a7740 only */
 enum GECMR_BIT {
        GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
 };
-#endif
 
 /* EDMR */
 enum DMAC_M_BIT {
@@ -251,13 +256,19 @@ enum EESR_BIT {
        EESR_CERF       = 0x00000001,
 };
 
+#define EESR_RX_CHECK          (EESR_FRC  | /* Frame recv */           \
+                                EESR_RMAF | /* Multicast address recv */ \
+                                EESR_RRF  | /* Bit frame recv */       \
+                                EESR_RTLF | /* Long frame recv */      \
+                                EESR_RTSF | /* Short frame recv */     \
+                                EESR_PRE  | /* PHY-LSI recv error */   \
+                                EESR_CERF)  /* Recv frame CRC error */
+
 #define DEFAULT_TX_CHECK       (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
                                 EESR_RTO)
 #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \
                                 EESR_RDE | EESR_RFRMER | EESR_ADE | \
                                 EESR_TFE | EESR_TDE | EESR_ECI)
-#define DEFAULT_TX_ERROR_CHECK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
-                                EESR_TFE)
 
 /* EESIPR */
 enum DMAC_IM_BIT {
@@ -299,11 +310,11 @@ enum FCFTR_BIT {
 #define DEFAULT_FIFO_F_D_RFF   (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
 #define DEFAULT_FIFO_F_D_RFD   (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
 
-/* Transfer descriptor bit */
+/* Transmit descriptor bit */
 enum TD_STS_BIT {
-       TD_TACT = 0x80000000,
-       TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
-       TD_TFP0 = 0x10000000,
+       TD_TACT = 0x80000000, TD_TDLE = 0x40000000,
+       TD_TFP1 = 0x20000000, TD_TFP0 = 0x10000000,
+       TD_TFE  = 0x08000000, TD_TWBI = 0x04000000,
 };
 #define TDF1ST TD_TFP1
 #define TDFEND TD_TFP0
@@ -450,6 +461,7 @@ struct sh_eth_cpu_data {
        void (*set_rate)(struct net_device *ndev);
 
        /* mandatory initialize value */
+       int register_type;
        unsigned long eesipr_value;
 
        /* optional initialize value */
@@ -463,9 +475,9 @@ struct sh_eth_cpu_data {
        /* interrupt checking mask */
        unsigned long tx_check;
        unsigned long eesr_err_check;
-       unsigned long tx_error_check;
 
        /* hardware features */
+       unsigned long irq_flags;        /* IRQ configuration flags */
        unsigned no_psr:1;              /* EtherC DO NOT have PSR */
        unsigned apr:1;                 /* EtherC have APR */
        unsigned mpr:1;                 /* EtherC have MPR */
@@ -478,6 +490,8 @@ struct sh_eth_cpu_data {
        unsigned no_ade:1;      /* E-DMAC DO NOT have ADE bit in EESR */
        unsigned hw_crc:1;      /* E-DMAC have CSMR */
        unsigned select_mii:1;  /* EtherC have RMII_MII (MII select register) */
+       unsigned shift_rd0:1;   /* shift Rx descriptor word 0 right by 16 */
+       unsigned rmiimode:1;    /* EtherC has RMIIMODE register */
 };
 
 struct sh_eth_private {
@@ -499,6 +513,7 @@ struct sh_eth_private {
        u32 cur_tx, dirty_tx;
        u32 rx_buf_sz;          /* Based on MTU+slack. */
        int edmac_endian;
+       struct napi_struct napi;
        /* MII transceiver section. */
        u32 phy_id;                                     /* PHY ID */
        struct mii_bus *mii_bus;        /* MDIO bus control */