#include <errno.h>
#include <fdtdec.h>
#include <fdt_support.h>
+#include <i2c.h>
#include <video_fb.h>
#include "videomodes.h"
#include "hitachi_tx18d42vm_lcd.h"
GraphicDevice graphic_device;
enum sunxi_monitor monitor;
unsigned int depth;
+ unsigned int fb_size;
} sunxi_display;
#ifdef CONFIG_VIDEO_HDMI
CCM_HDMI_CTRL_PLL3);
/* Set ahb gating to pass */
-#ifdef CONFIG_MACH_SUN6I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
#endif
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
-#ifdef CONFIG_MACH_SUN6I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
#endif
clock_set_pll3(0);
sunxi_frontend_init();
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
/* Reset off */
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
#endif
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
/* Reset off */
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
#else
setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
/* Clock on */
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+ setbits_le32(&ccm->ahb_reset2_cfg, 1 << AHB_RESET_OFFSET_LVDS);
+#else
setbits_le32(&ccm->lvds_clk_cfg, CCM_LVDS_CTRL_RST);
+#endif
#endif
/* Init lcdc */
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+ udelay(2); /* delay at least 1200 ns */
+ setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB);
+ udelay(2); /* delay at least 1200 ns */
+ setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC);
+ if (sunxi_display.depth == 18)
+ setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7));
+ else
+ setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf));
+#else
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
udelay(2); /* delay at least 1200 ns */
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);
setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);
setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
#endif
+#endif
}
static void sunxi_lcdc_panel_enable(void)
{
- int pin;
+ int pin, reset_pin;
/*
* Start with backlight disabled to avoid the screen flashing to
* white while the lcd inits.
*/
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
- if (pin != -1) {
+ if (pin >= 0) {
gpio_request(pin, "lcd_backlight_enable");
gpio_direction_output(pin, 0);
}
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
- if (pin != -1) {
+ if (pin >= 0) {
gpio_request(pin, "lcd_backlight_pwm");
gpio_direction_output(pin, PWM_OFF);
}
+ reset_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_RESET);
+ if (reset_pin >= 0) {
+ gpio_request(reset_pin, "lcd_reset");
+ gpio_direction_output(reset_pin, 0); /* Assert reset */
+ }
+
/* Give the backlight some time to turn off and power up the panel. */
mdelay(40);
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER);
- if (pin != -1) {
+ if (pin >= 0) {
gpio_request(pin, "lcd_power");
gpio_direction_output(pin, 1);
}
+
+ if (reset_pin >= 0)
+ gpio_direction_output(reset_pin, 1); /* De-assert reset */
}
static void sunxi_lcdc_backlight_enable(void)
mdelay(40);
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
- if (pin != -1)
+ if (pin >= 0)
gpio_direction_output(pin, 1);
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
- if (pin != -1)
+ if (pin >= 0)
gpio_direction_output(pin, PWM_ON);
}
return (delay > 30) ? 30 : delay;
}
-static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode)
+static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
+ bool for_ext_vga_dac)
{
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++)
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LCD0);
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
- sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LVDS0);
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LVDS0);
#endif
sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
val = (sunxi_display.depth == 18) ? 1 : 0;
- writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val), &lcdc->tcon0_lvds_intf);
+ writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) |
+ SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf);
#endif
if (sunxi_display.depth == 18 || sunxi_display.depth == 16) {
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
val |= SUNXI_LCDC_TCON_VSYNC_MASK;
+
+#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
+ if (for_ext_vga_dac)
+ val = 0;
+#endif
writel(val, &lcdc->tcon0_io_polarity);
writel(0, &lcdc->tcon0_io_tristate);
&lcdc->tcon1_timing_sync);
if (use_portd_hvsync) {
- sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD0_LCD0);
- sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD0_LCD0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);
val = 0;
if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
static void sunxi_drc_init(void)
{
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* On sun6i the drc must be clocked even when in pass-through mode */
+#ifdef CONFIG_MACH_SUN8I_A33
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
+#endif
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
#endif
int pin;
pin = sunxi_name_to_gpio(CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN);
- if (pin != -1) {
+ if (pin >= 0) {
gpio_request(pin, "vga_enable");
gpio_direction_output(pin, 1);
}
mdelay(50); /* Wait for lcd controller power on */
hitachi_tx18d42vm_init();
}
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
+ unsigned int orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_VIDEO_LCD_I2C_BUS);
+ i2c_reg_write(0x5c, 0x04, 0x42); /* Turn on the LCD */
+ i2c_set_bus_num(orig_i2c_bus);
+ }
sunxi_composer_mode_set(mode, address);
- sunxi_lcdc_tcon0_mode_set(mode);
+ sunxi_lcdc_tcon0_mode_set(mode, false);
sunxi_composer_enable();
sunxi_lcdc_enable();
#ifdef CONFIG_VIDEO_LCD_SSD2828
sunxi_vga_enable();
#elif defined CONFIG_VIDEO_VGA_VIA_LCD
sunxi_composer_mode_set(mode, address);
- sunxi_lcdc_tcon0_mode_set(mode);
+ sunxi_lcdc_tcon0_mode_set(mode, true);
sunxi_composer_enable();
sunxi_lcdc_enable();
sunxi_vga_external_dac_enable();
return NULL; /* never reached */
}
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return gd->ram_top - CONFIG_SUNXI_MAX_FB_SIZE;
+}
+
void *video_hw_init(void)
{
static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
memset(&sunxi_display, 0, sizeof(struct sunxi_display));
- printf("Reserved %dkB of RAM for Framebuffer.\n",
- CONFIG_SUNXI_FB_SIZE >> 10);
- gd->fb_base = gd->ram_top;
-
video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
&sunxi_display.depth, &options);
#ifdef CONFIG_VIDEO_HDMI
mode->yres, sunxi_get_mon_desc(sunxi_display.monitor));
}
+ sunxi_display.fb_size =
+ (mode->xres * mode->yres * 4 + 0xfff) & ~0xfff;
+ if (sunxi_display.fb_size > CONFIG_SUNXI_MAX_FB_SIZE) {
+ printf("Error need %dkB for fb, but only %dkB is reserved\n",
+ sunxi_display.fb_size >> 10,
+ CONFIG_SUNXI_MAX_FB_SIZE >> 10);
+ return NULL;
+ }
+
+ gd->fb_base = gd->bd->bi_dram[0].start +
+ gd->bd->bi_dram[0].size - sunxi_display.fb_size;
sunxi_engines_init();
sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
{
static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
int offset, ret;
+ u64 start, size;
const char *pipeline = NULL;
#ifdef CONFIG_MACH_SUN4I
return 0; /* Keep older kernels working */
}
+ /*
+ * Do not report the framebuffer as free RAM to the OS, note we cannot
+ * use fdt_add_mem_rsv() here, because then it is still seen as RAM,
+ * and e.g. Linux refuses to iomap RAM on ARM, see:
+ * linux/arch/arm/mm/ioremap.c around line 301.
+ */
+ start = gd->bd->bi_dram[0].start;
+ size = gd->bd->bi_dram[0].size - sunxi_display.fb_size;
+ ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
+ if (ret) {
+ eprintf("Cannot setup simplefb: Error reserving memory\n");
+ return ret;
+ }
+
ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
graphic_device->winSizeX, graphic_device->winSizeY,
graphic_device->winSizeX * graphic_device->gdfBytesPP,
projects / karo-tx-uboot.git / blobdiff