karo: tx51,tx53,tx6: remove obsolete CONFIG_SYS_FSL_ESDHC_NUM definition

[karo-tx-uboot.git] / include / configs / MIP405.h

diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 58764d0dfbd2b63c7342f9dfec1829ca2accdc7c..c535dbeaae1dfa5bf737daba8826f8502001874d 100644 (file)
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -2,23 +2,7 @@
  * (C) Copyright 2001, 2002
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+ 
  */
 
 /*
@@ -91,7 +75,6 @@
 
 
 #define         CONFIG_SYS_HUSH_PARSER
-#define         CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 /**************************************************************
  * I2C Stuff:
  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
@@ -99,10 +82,11 @@
  * The Atmel EEPROM uses 16Bit addressing.
  ***************************************************************/
 
-#define CONFIG_HARD_I2C                        /* I2c with hardware support */
-#define CONFIG_PPC4XX_I2C              /* use PPC4xx driver            */
-#define CONFIG_SYS_I2C_SPEED           50000   /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE           0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0          50000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0          0x7F
 
 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x53    /* EEPROM 24C128/256            */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2       /* Bytes of address             */
@@ -207,6 +191,7 @@
 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 
 #define CONFIG_PCI                     /* include pci support          */
+#define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host        */
 #define CONFIG_PCI_PNP                 /* pci plug-and-play            */
                                        /* resource configuration       */
@@ -239,11 +224,17 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks           */
-#define CONFIG_SYS_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
+#define CONFIG_SYS_UPDATE_FLASH_SIZE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_FLASH_SHOW_PROGRESS     45
 
-#define CONFIG_SYS_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+#define CONFIG_SYS_MAX_FLASH_SECT      256
 
 /*
  * JFFS2 partitions
@@ -291,6 +282,7 @@
 #define FLASH_SIZE_PRELIM       3  /* maximal flash FLASH size bank #0 */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_BOARD_EARLY_INIT_R
 
 /* Peripheral Bus Mapping */
 #define PER_PLD_ADDR           0xF4000000 /* smallest window is 1MByte 0x10 0000*/
@@ -308,9 +300,8 @@
 #define CONFIG_SYS_OCM_DATA_ADDR       0xF0000000
 #define CONFIG_SYS_OCM_DATA_SIZE       0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_OCM_DATA_ADDR        /* inside of On Chip SRAM    */
-#define CONFIG_SYS_INIT_RAM_END        CONFIG_SYS_OCM_DATA_SIZE        /* End of On Chip SRAM         */
-#define CONFIG_SYS_GBL_DATA_SIZE       64              /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE       CONFIG_SYS_OCM_DATA_SIZE        /* Size of On Chip SRAM        */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 /* reserve some memory for POST and BOOT limit info */
 #define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 
@@ -335,7 +326,6 @@
 #define CONFIG_PHY_ADDR                1       /* PHY address                  */
 #define CONFIG_PHY_RESET_DELAY 300     /* Intel LXT971A needs this */
 #define CONFIG_PHY_CMD_DELAY   40      /* Intel LXT971A needs this */
-#define CONFIG_NET_MULTI
 /************************************************************
  * RTC
  ***********************************************************/