Remove last remanants of unused CONFIG_I2C_CMD_TREE

[karo-tx-uboot.git] / include / configs / P2020DS.h

diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index a39ff26a7a2a9d024e6f4be8c1f2b38ae6dfb6c3..70ab96f33580a2c96b4094517ebafc00e9746975 100644 (file)
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -46,6 +46,7 @@
 #define CONFIG_SYS_PCI_64BIT   1       /* enable 64-bit PCI resources */
 
 #define CONFIG_FSL_LAW         1       /* Use common FSL init code */
+#define CONFIG_E1000           1       /* Defind e1000 pci Ethernet card*/
 
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
@@ -109,7 +110,9 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 #define CONFIG_FSL_DDR3                1
 #undef CONFIG_FSL_DDR_INTERACTIVE
 
-// #define     CONFIG_DDR_ECC /* ECC will be enabled based on perf_mode environment variable */
+/* ECC will be enabled based on perf_mode environment variable */
+/* #define     CONFIG_DDR_ECC */
+
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE  0xDeadBeef
 
@@ -125,7 +128,6 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 #define SPD_EEPROM_ADDRESS1    0x51    /* CTLR 0 DIMM 0 */
 
 /* These are used when DDR doesn't use SPD.  */
-//#define CONFIG_SYS_SDRAM_SIZE                512             /* DDR is 512MB */
 #define CONFIG_SYS_SDRAM_SIZE          1024            /* DDR is 1GB */
 
 /* Default settings for "stable" mode */
@@ -410,7 +412,6 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 #define CONFIG_HARD_I2C                /* I2C with hardware support */
 #undef CONFIG_SOFT_I2C         /* I2C bit-banged */
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED           400000  /* I2C speed and slave address */
 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 #define CONFIG_SYS_I2C_SLAVE           0x7F
@@ -437,7 +438,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT      0x80000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE3_MEM_BUS       0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS      0xc00000000ull
 #else
 #define CONFIG_SYS_PCIE3_MEM_BUS       0x80000000
@@ -456,7 +457,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS       0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
 #else
 #define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
@@ -475,7 +476,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT      0xc0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS       0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      0xc40000000ull
 #else
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xc0000000
@@ -517,12 +518,6 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 #undef CONFIG_TULIP
 #define CONFIG_RTL8139
 
-#ifdef CONFIG_RTL8139
-/* This macro is used by RTL8139 but not defined in PPC architecture */
-#define KSEG1ADDR(x)           (x)
-#define _IO_BASE       0x00000000
-#endif
-
 #ifndef CONFIG_PCI_PNP
        #define PCI_ENET0_IOADDR        CONFIG_SYS_PCIE3_IO_BUS
        #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCIE3_IO_BUS