* Add comment about non-GPL character of standalone applications to

[karo-tx-uboot.git] / include / mpc5xxx.h

diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index 4218b050fc739326f000109adb4088583115aba4..e5c8c02ad203936f3c80a8e384a23980ca3337de 100644 (file)
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -40,6 +40,15 @@
 /* Exception offsets (PowerPC standard) */
 #define EXC_OFF_SYS_RESET      0x0100
 
+/* useful macros for manipulating CSx_START/STOP */
+#if defined(CONFIG_MGT5100)
+#define START_REG(start)       ((start) >> 15)
+#define STOP_REG(start, size)  (((start) + (size) - 1) >> 15)
+#elif defined(CONFIG_MPC5200)
+#define START_REG(start)       ((start) >> 16)
+#define STOP_REG(start, size)  (((start) + (size) - 1) >> 16)
+#endif
+
 /* Internal memory map */
 
 #define MPC5XXX_CS0_START      (CFG_MBAR + 0x0004)
@@ -80,7 +89,9 @@
 #define MPC5XXX_ICTL           (CFG_MBAR + 0x0500)
 #define MPC5XXX_GPT            (CFG_MBAR + 0x0600)
 #define MPC5XXX_GPIO           (CFG_MBAR + 0x0b00)
+#define MPC5XXX_WU_GPIO         (CFG_MBAR + 0x0c00)
 #define MPC5XXX_PCI            (CFG_MBAR + 0x0d00)
+#define MPC5XXX_USB            (CFG_MBAR + 0x1000)
 #define MPC5XXX_SDMA           (CFG_MBAR + 0x1200)
 #define MPC5XXX_XLBARB         (CFG_MBAR + 0x1f00)
 
@@ -98,6 +109,10 @@
 #endif
 
 #define        MPC5XXX_FEC             (CFG_MBAR + 0x3000)
+#define MPC5XXX_ATA             (CFG_MBAR + 0x3A00)
+
+#define MPC5XXX_I2C1           (CFG_MBAR + 0x3D00)
+#define MPC5XXX_I2C2           (CFG_MBAR + 0x3D40)
 
 #if defined(CONFIG_MGT5100)
 #define MPC5XXX_SRAM           (CFG_MBAR + 0x4000)
@@ -120,6 +135,7 @@
 #define MPC5XXX_CDM_JTAGID     (MPC5XXX_CDM + 0x0000)
 #define MPC5XXX_CDM_PORCFG     (MPC5XXX_CDM + 0x0004)
 #define MPC5XXX_CDM_CFG                (MPC5XXX_CDM + 0x000c)
+#define MPC5XXX_CDM_48_FDC     (MPC5XXX_CDM + 0x0010)
 #define MPC5XXX_CDM_SRESET     (MPC5XXX_CDM + 0x0020)
 
 /* Local Plus Bus interface */
@@ -139,9 +155,39 @@
 #define MPC5XXX_CS_DEADCYCLE   (MPC5XXX_LPB + 0x002c)
 #endif
 
+#if defined(CONFIG_MPC5200)
+/* XLB Arbiter registers */
+#define MPC5XXX_XLBARB_CFG             (MPC5XXX_XLBARB + 0x40)
+#define MPC5XXX_XLBARB_MPRIEN  (MPC5XXX_XLBARB + 0x64)
+#define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68)
+#endif
+
 /* GPIO registers */
 #define MPC5XXX_GPS_PORT_CONFIG        (MPC5XXX_GPIO + 0x0000)
 
+/* Standard GPIO registers (simple, output only and simple interrupt */
+#define MPC5XXX_GPIO_ENABLE     (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_GPIO_ODE        (MPC5XXX_GPIO + 0x0008)
+#define MPC5XXX_GPIO_DIR        (MPC5XXX_GPIO + 0x000c)
+#define MPC5XXX_GPIO_DATA_O     (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_GPIO_DATA_I     (MPC5XXX_GPIO + 0x0014)
+#define MPC5XXX_GPIO_OO_ENABLE  (MPC5XXX_GPIO + 0x0018)
+#define MPC5XXX_GPIO_OO_DATA    (MPC5XXX_GPIO + 0x001C)
+#define MPC5XXX_GPIO_SI_ENABLE  (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_GPIO_SI_ODE     (MPC5XXX_GPIO + 0x0024)
+#define MPC5XXX_GPIO_SI_DIR     (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_GPIO_SI_DATA    (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_GPIO_SI_IEN     (MPC5XXX_GPIO + 0x0030)
+#define MPC5XXX_GPIO_SI_ITYPE   (MPC5XXX_GPIO + 0x0034)
+#define MPC5XXX_GPIO_SI_MEN     (MPC5XXX_GPIO + 0x0038)
+#define MPC5XXX_GPIO_SI_STATUS  (MPC5XXX_GPIO + 0x003C)
+
+/* WakeUp GPIO registers */
+#define MPC5XXX_WU_GPIO_ENABLE  (MPC5XXX_WU_GPIO + 0x0000)
+#define MPC5XXX_WU_GPIO_ODE     (MPC5XXX_WU_GPIO + 0x0004)
+#define MPC5XXX_WU_GPIO_DIR     (MPC5XXX_WU_GPIO + 0x0008)
+#define MPC5XXX_WU_GPIO_DATA    (MPC5XXX_WU_GPIO + 0x000c)
+
 /* PCI registers */
 #define MPC5XXX_PCI_CMD                (MPC5XXX_PCI + 0x04)
 #define MPC5XXX_PCI_CFG                (MPC5XXX_PCI + 0x0c)
@@ -188,6 +234,30 @@
 #define MPC5XXX_GPT0_ENABLE            (MPC5XXX_GPT + 0x0)
 #define MPC5XXX_GPT0_COUNTER           (MPC5XXX_GPT + 0x4)
 
+/* ATA registers */
+#define MPC5XXX_ATA_HOST_CONFIG         (MPC5XXX_ATA + 0x0000)
+#define MPC5XXX_ATA_PIO1                (MPC5XXX_ATA + 0x0008)
+#define MPC5XXX_ATA_PIO2                (MPC5XXX_ATA + 0x000C)
+#define MPC5XXX_ATA_SHARE_COUNT         (MPC5XXX_ATA + 0x002C)
+
+/* I2Cn control register bits */
+#define I2C_EN         0x80
+#define I2C_IEN                0x40
+#define I2C_STA                0x20
+#define I2C_TX         0x10
+#define I2C_TXAK       0x08
+#define I2C_RSTA       0x04
+#define I2C_INIT_MASK  (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
+
+/* I2Cn status register bits */
+#define I2C_CF         0x80
+#define I2C_AAS                0x40
+#define I2C_BB         0x20
+#define I2C_AL         0x10
+#define I2C_SRW                0x04
+#define I2C_IF         0x02
+#define I2C_RXAK       0x01
+
 /* Programmable Serial Controller (PSC) status register bits */
 #define PSC_SR_CDE             0x0080
 #define PSC_SR_RXRDY           0x0100
@@ -248,6 +318,15 @@
 #define PSC_MODE_ONE_STOP              0x07
 #define PSC_MODE_TWO_STOP              0x0f
 
+/* ATA config fields */
+#define MPC5xxx_ATA_HOSTCONF_SMR       0x80000000UL    /* State machine
+                                                          reset */
+#define MPC5xxx_ATA_HOSTCONF_FR                0x40000000UL    /* FIFO Reset */
+#define MPC5xxx_ATA_HOSTCONF_IE                0x02000000UL    /* Enable interrupt
+                                                          in PIO */
+#define MPC5xxx_ATA_HOSTCONF_IORDY     0x01000000UL    /* Drive supports
+                                                          IORDY protocol */
+
 #ifndef __ASSEMBLY__
 struct mpc5xxx_psc {
        volatile u8     mode;           /* PSC + 0x00 */
@@ -496,6 +575,14 @@ struct mpc5xxx_sdma {
        volatile u32 EU37;              /* SDMA + 0xfc */
 };
 
+struct mpc5xxx_i2c {
+       volatile u32 madr;              /* I2Cn + 0x00 */
+       volatile u32 mfdr;              /* I2Cn + 0x04 */
+       volatile u32 mcr;               /* I2Cn + 0x08 */
+       volatile u32 msr;               /* I2Cn + 0x0C */
+       volatile u32 mdr;               /* I2Cn + 0x10 */
+};
+
 /* function prototypes */
 void loadtask(int basetask, int tasks);