Fix build errors when CONFIG_LOGBUFFER and CONFIG_FIT are enabled

[karo-tx-uboot.git] / include / pci.h

diff --git a/include/pci.h b/include/pci.h
index 458be233e4ac5083107d3ed3a3ecd692fecae2d1..8e5dacc0df6cac054670e8b2238a485dbd02bd5f 100644 (file)
--- a/include/pci.h
+++ b/include/pci.h
@@ -160,6 +160,21 @@
 #define  PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
 #define  PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
 
+/* From 440ep */
+#define PCI_ERREN       0x48     /* Error Enable */
+#define PCI_ERRSTS      0x49     /* Error Status */
+#define PCI_BRDGOPT1    0x4A     /* PCI Bridge Options 1 */
+#define PCI_PLBSESR0    0x4C     /* PCI PLB Slave Error Syndrome 0 */
+#define PCI_PLBSESR1    0x50     /* PCI PLB Slave Error Syndrome 1 */
+#define PCI_PLBSEAR     0x54     /* PCI PLB Slave Error Address */
+#define PCI_CAPID       0x58     /* Capability Identifier */
+#define PCI_NEXTITEMPTR 0x59     /* Next Item Pointer */
+#define PCI_PMC         0x5A     /* Power Management Capabilities */
+#define PCI_PMCSR       0x5C     /* Power Management Control Status */
+#define PCI_PMCSRBSE    0x5E     /* PMCSR PCI to PCI Bridge Support Extensions */
+#define PCI_BRDGOPT2    0x60     /* PCI Bridge Options 2 */
+#define PCI_PMSCRR      0x64     /* Power Management State Change Request Re. */
+
 /* Header type 2 (CardBus bridges) */
 #define PCI_CB_CAPABILITY_LIST 0x14
 /* 0x15 reserved */
@@ -255,6 +270,15 @@
 #define  PCI_AGP_COMMAND_RATE1 0x0001  /* Use 4x rate */
 #define PCI_AGP_SIZEOF         12
 
+/* PCI-X registers */
+
+#define  PCI_X_CMD_DPERR_E      0x0001  /* Data Parity Error Recovery Enable */
+#define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
+#define  PCI_X_CMD_MAX_READ     0x0000  /* Max Memory Read Byte Count */
+#define  PCI_X_CMD_MAX_SPLIT    0x0030  /* Max Outstanding Split Transactions */
+#define  PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
+
+
 /* Slot Identification */
 
 #define PCI_SID_ESR            2       /* Expansion Slot Register */
@@ -278,6 +302,12 @@
 #define PCI_MAX_PCI_DEVICES    32
 #define PCI_MAX_PCI_FUNCTIONS  8
 
+#define PCI_DCR                0x54    /* PCIe Device Control Register */
+#define PCI_DSR                0x56    /* PCIe Device Status Register */
+#define PCI_LSR                0x5e    /* PCIe Link Status Register */
+#define PCI_LTSSM      0x404   /* PCIe Link Training, Status State Machine */
+#define  PCI_LTSSM_L0  0x16    /* L0 state */
+
 /* Include the ID list */
 
 #include <pci_ids.h>
@@ -294,6 +324,7 @@ struct pci_region {
 #define PCI_REGION_MEM         0x00000000      /* PCI memory space */
 #define PCI_REGION_IO          0x00000001      /* PCI IO space */
 #define PCI_REGION_TYPE                0x00000001
+#define PCI_REGION_PREFETCH    0x00000008      /* prefetchable PCI memory */
 
 #define PCI_REGION_MEMORY      0x00000100      /* System memory */
 #define PCI_REGION_RO          0x00000200      /* Read-only memory */
@@ -336,8 +367,8 @@ struct pci_config_table {
        unsigned long priv[3];
 };
 
-extern void pci_cfgfunc_nothing(struct pci_controller* hose, pci_dev_t dev,
-                               struct pci_config_table *);
+extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
+                                  struct pci_config_table *);
 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
                                      struct pci_config_table *);
 
@@ -371,7 +402,7 @@ struct pci_controller {
        int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
 
        /* Used by auto config */
-       struct pci_region *pci_mem, *pci_io;
+       struct pci_region *pci_mem, *pci_io, *pci_prefetch;
 
        /* Used by ppc405 autoconfig*/
        struct pci_region *pci_fb;
@@ -457,6 +488,7 @@ extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, un
 extern void pciauto_setup_device(struct pci_controller *hose,
                                 pci_dev_t dev, int bars_num,
                                 struct pci_region *mem,
+                                struct pci_region *prefetch,
                                 struct pci_region *io);
 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 
@@ -475,4 +507,7 @@ extern int pci_hose_config_device(struct pci_controller *hose,
 extern void pci_mpc824x_init (struct pci_controller *hose);
 #endif
 
+#ifdef CONFIG_MPC85xx
+extern void pci_mpc85xx_init (struct pci_controller *hose);
+#endif
 #endif /* _PCI_H */