powerpc: add support for the Freescale P1022DS reference board

[karo-tx-uboot.git] / include / ppc4xx.h

diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 086f8fb7ee3a7424cb6057bd92876c60d5709052..ee30a4ca3de8ae2450ae659af3db66ac5307df3e 100644 (file)
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -100,12 +100,6 @@
 #endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
 
 #if defined(CONFIG_440)
-/*
- * Enable long long (%ll ...) printf format on 440 PPC's since most of
- * them support 36bit physical addressing
- */
-#define CONFIG_SYS_64BIT_VSPRINTF
-#define CONFIG_SYS_64BIT_STRTOUL
 #include <ppc440.h>
 #else
 #include <ppc405.h>
@@ -136,12 +130,12 @@
  * Common stuff for 4xx (405 and 440)
  */
 
-#define EXC_OFF_SYS_RESET      0x0100  /* System reset                         */
+#define EXC_OFF_SYS_RESET      0x0100  /* System reset                 */
 #define _START_OFFSET          (EXC_OFF_SYS_RESET + 0x2000)
 
 #define RESET_VECTOR   0xfffffffc
-#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
-                                                    line aligned data. */
+#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
+                                               cache line aligned data. */
 
 #define CPR0_DCR_BASE  0x0C
 #define CPR0_CFGADDR   (CPR0_DCR_BASE + 0x0)
@@ -162,17 +156,25 @@
 /*
  * Macros for indirect DCR access
  */
-#define mtcpr(reg, d)  do { mtdcr(CPR0_CFGADDR,reg);mtdcr(CPR0_CFGDATA,d); } while (0)
-#define mfcpr(reg, d)  do { mtdcr(CPR0_CFGADDR,reg);d = mfdcr(CPR0_CFGDATA); } while (0)
-
-#define mtebc(reg, d)  do { mtdcr(EBC0_CFGADDR,reg);mtdcr(EBC0_CFGDATA,d); } while (0)
-#define mfebc(reg, d)  do { mtdcr(EBC0_CFGADDR,reg);d = mfdcr(EBC0_CFGDATA); } while (0)
-
-#define mtsdram(reg, d)        do { mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,d); } while (0)
-#define mfsdram(reg, d)        do { mtdcr(SDRAM0_CFGADDR,reg);d = mfdcr(SDRAM0_CFGDATA); } while (0)
-
-#define mtsdr(reg, d)  do { mtdcr(SDR0_CFGADDR,reg);mtdcr(SDR0_CFGDATA,d); } while (0)
-#define mfsdr(reg, d)  do { mtdcr(SDR0_CFGADDR,reg);d = mfdcr(SDR0_CFGDATA); } while (0)
+#define mtcpr(reg, d)  \
+  do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
+#define mfcpr(reg, d)  \
+  do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
+
+#define mtebc(reg, d)  \
+  do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
+#define mfebc(reg, d)  \
+  do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
+
+#define mtsdram(reg, d)        \
+  do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
+#define mfsdram(reg, d)        \
+  do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
+
+#define mtsdr(reg, d)  \
+  do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
+#define mfsdr(reg, d)  \
+  do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
 
 #ifndef __ASSEMBLY__
 
@@ -213,6 +215,8 @@ static inline void set_mcsr(u32 val)
        asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
 }
 
+int ppc4xx_pci_sync_clock_config(u32 async);
+
 #endif /* __ASSEMBLY__ */
 
 /* for multi-cpu support */