TI:am33xx: Create common config files for TI ARMv7 platforms, and AM33xx

[karo-tx-uboot.git] / include / xilinx.h

diff --git a/include/xilinx.h b/include/xilinx.h
index bcfe76d81ef07bf0050ed5b699e4d244dd3f5d30..00a585e5fc311650e7d981c507cd3310c2948d1e 100644 (file)
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -2,24 +2,7 @@
  * (C) Copyright 2002
  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <fpga.h>
@@ -27,30 +10,6 @@
 #ifndef _XILINX_H_
 #define _XILINX_H_
 
-/* Xilinx Model definitions
- *********************************************************************/
-#define CONFIG_SYS_SPARTAN2                    CONFIG_SYS_FPGA_DEV( 0x1 )
-#define CONFIG_SYS_VIRTEX_E                    CONFIG_SYS_FPGA_DEV( 0x2 )
-#define CONFIG_SYS_VIRTEX2                     CONFIG_SYS_FPGA_DEV( 0x4 )
-#define CONFIG_SYS_SPARTAN3                    CONFIG_SYS_FPGA_DEV( 0x8 )
-#define CONFIG_SYS_ZYNQ                                CONFIG_SYS_FPGA_DEV(0x10)
-#define CONFIG_SYS_XILINX_SPARTAN2     (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN2)
-#define CONFIG_SYS_XILINX_VIRTEX_E     (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX_E)
-#define CONFIG_SYS_XILINX_VIRTEX2      (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX2)
-#define CONFIG_SYS_XILINX_SPARTAN3     (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN3)
-#define CONFIG_SYS_XILINX_ZYNQ (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_ZYNQ)
-/* XXX - Add new models here */
-
-
-/* Xilinx Interface definitions
- *********************************************************************/
-#define CONFIG_SYS_XILINX_IF_SS        CONFIG_SYS_FPGA_IF( 0x1 )       /* slave serial         */
-#define CONFIG_SYS_XILINX_IF_MS        CONFIG_SYS_FPGA_IF( 0x2 )       /* master serial        */
-#define CONFIG_SYS_XILINX_IF_SP        CONFIG_SYS_FPGA_IF( 0x4 )       /* slave parallel       */
-#define CONFIG_SYS_XILINX_IF_JTAG      CONFIG_SYS_FPGA_IF( 0x8 )       /* jtag                 */
-#define CONFIG_SYS_XILINX_IF_MSM       CONFIG_SYS_FPGA_IF( 0x10 )      /* master selectmap     */
-#define CONFIG_SYS_XILINX_IF_SSM       CONFIG_SYS_FPGA_IF( 0x20 )      /* slave selectmap      */
-
 /* Xilinx types
  *********************************************************************/
 typedef enum {                 /* typedef Xilinx_iface */