X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fam33xx%2Femif4.c;h=b2d7c0d95621495f3ad3c6c8beb3281217681f3d;hb=5675b509165b67465a20e5cf71e07f40b449ef0c;hp=e04e97067896b83703f995d1b92fe8b958198498;hpb=c48c89543310bae633c7aa44a0fc94b9c97c8453;p=karo-tx-uboot.git diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index e04e970678..b2d7c0d956 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -27,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; -struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR; -struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR; -struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; - int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ @@ -48,48 +44,81 @@ void dram_init_banksize(void) #ifdef CONFIG_SPL_BUILD +static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR; +static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; + static const struct ddr_data ddr2_data = { .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)), - .datardsratio1 = DDR2_RD_DQS>>2, .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)), - .datawdsratio1 = DDR2_WR_DQS>>2, .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)), - .datawiratio1 = DDR2_PHY_WRLVL>>2, .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)), - .datagiratio1 = DDR2_PHY_GATELVL>>2, .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)), - .datafwsratio1 = DDR2_PHY_FIFO_WE>>2, .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)), - .datawrsratio1 = DDR2_PHY_WR_DATA>>2, + .datauserank0delay = DDR2_PHY_RANK0_DELAY, .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr2_cmd_ctrl_data = { .cmd0csratio = DDR2_RATIO, - .cmd0csforce = CMD_FORCE, - .cmd0csdelay = CMD_DELAY, .cmd0dldiff = DDR2_DLL_LOCK_DIFF, .cmd0iclkout = DDR2_INVERT_CLKOUT, .cmd1csratio = DDR2_RATIO, - .cmd1csforce = CMD_FORCE, - .cmd1csdelay = CMD_DELAY, .cmd1dldiff = DDR2_DLL_LOCK_DIFF, .cmd1iclkout = DDR2_INVERT_CLKOUT, .cmd2csratio = DDR2_RATIO, - .cmd2csforce = CMD_FORCE, - .cmd2csdelay = CMD_DELAY, .cmd2dldiff = DDR2_DLL_LOCK_DIFF, .cmd2iclkout = DDR2_INVERT_CLKOUT, }; +static const struct emif_regs ddr2_emif_reg_data = { + .sdram_config = DDR2_EMIF_SDCFG, + .ref_ctrl = DDR2_EMIF_SDREF, + .sdram_tim1 = DDR2_EMIF_TIM1, + .sdram_tim2 = DDR2_EMIF_TIM2, + .sdram_tim3 = DDR2_EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY, +}; + +static const struct ddr_data ddr3_data = { + .datardsratio0 = DDR3_RD_DQS, + .datawdsratio0 = DDR3_WR_DQS, + .datafwsratio0 = DDR3_PHY_FIFO_WE, + .datawrsratio0 = DDR3_PHY_WR_DATA, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = DDR3_RATIO, + .cmd0dldiff = DDR3_DLL_LOCK_DIFF, + .cmd0iclkout = DDR3_INVERT_CLKOUT, + + .cmd1csratio = DDR3_RATIO, + .cmd1dldiff = DDR3_DLL_LOCK_DIFF, + .cmd1iclkout = DDR3_INVERT_CLKOUT, + + .cmd2csratio = DDR3_RATIO, + .cmd2dldiff = DDR3_DLL_LOCK_DIFF, + .cmd2iclkout = DDR3_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = DDR3_EMIF_SDCFG, + .ref_ctrl = DDR3_EMIF_SDREF, + .sdram_tim1 = DDR3_EMIF_TIM1, + .sdram_tim2 = DDR3_EMIF_TIM2, + .sdram_tim3 = DDR3_EMIF_TIM3, + .zq_config = DDR3_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY, +}; + static void config_vtp(void) { writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE, @@ -105,75 +134,46 @@ static void config_vtp(void) ; } -static void config_emif_ddr2(void) -{ - int ret; - struct sdram_config cfg; - struct sdram_timing tmg; - struct ddr_phy_control phyc; - - /* Program EMIF0 CFG Registers */ - phyc.reg = DDR2_EMIF_READ_LATENCY; - phyc.reg_sh = DDR2_EMIF_READ_LATENCY; - phyc.reg2 = DDR2_EMIF_READ_LATENCY; - - tmg.time1 = DDR2_EMIF_TIM1; - tmg.time1_sh = DDR2_EMIF_TIM1; - tmg.time2 = DDR2_EMIF_TIM2; - tmg.time2_sh = DDR2_EMIF_TIM2; - tmg.time3 = DDR2_EMIF_TIM3; - tmg.time3_sh = DDR2_EMIF_TIM3; - - cfg.sdrcr = DDR2_EMIF_SDCFG; - cfg.sdrcr2 = DDR2_EMIF_SDCFG; - cfg.refresh = DDR2_EMIF_SDREF; - cfg.refresh_sh = DDR2_EMIF_SDREF; - - /* Program EMIF instance */ - ret = config_ddr_phy(&phyc); - if (ret < 0) - printf("Couldn't configure phyc\n"); - - - ret = set_sdram_timings(&tmg); - if (ret < 0) - printf("Couldn't configure timings\n"); - - ret = config_sdram(&cfg); - if (ret < 0) - printf("Couldn't configure SDRAM\n"); -} - void config_ddr(short ddr_type) { - struct ddr_ioctrl ioctrl; - - enable_emif_clocks(); + int ddr_pll, ioctrl_val; + const struct emif_regs *emif_regs; + const struct ddr_data *ddr_data; + const struct cmd_control *cmd_ctrl_data; if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) { - ddr_pll_config(266); - config_vtp(); - - config_cmd_ctrl(&ddr2_cmd_ctrl_data); - - config_ddr_data(0, &ddr2_data); - config_ddr_data(1, &ddr2_data); + ddr_pll = 266; + cmd_ctrl_data = &ddr2_cmd_ctrl_data; + ddr_data = &ddr2_data; + ioctrl_val = DDR2_IOCTRL_VALUE; + emif_regs = &ddr2_emif_reg_data; + } else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) { + ddr_pll = 303; + cmd_ctrl_data = &ddr3_cmd_ctrl_data; + ddr_data = &ddr3_data; + ioctrl_val = DDR3_IOCTRL_VALUE; + emif_regs = &ddr3_emif_reg_data; + } else { + puts("Unknown memory type"); + hang(); + } - writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0); - writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0); + enable_emif_clocks(); + ddr_pll_config(ddr_pll); + config_vtp(); + config_cmd_ctrl(cmd_ctrl_data); - ioctrl.cmd1ctl = DDR2_IOCTRL_VALUE; - ioctrl.cmd2ctl = DDR2_IOCTRL_VALUE; - ioctrl.cmd3ctl = DDR2_IOCTRL_VALUE; - ioctrl.data1ctl = DDR2_IOCTRL_VALUE; - ioctrl.data2ctl = DDR2_IOCTRL_VALUE; + config_ddr_data(0, ddr_data); + config_ddr_data(1, ddr_data); - config_io_ctrl(&ioctrl); + config_io_ctrl(ioctrl_val); - /* Set CKE to be controlled by EMIF/DDR PHY */ - writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); + /* Set CKE to be controlled by EMIF/DDR PHY */ + writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); - config_emif_ddr2(); - } + /* Program EMIF instance */ + config_ddr_phy(emif_regs); + set_sdram_timings(emif_regs); + config_sdram(emif_regs); } #endif