X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=board%2Fatmel%2Fat91sam9261ek%2Fat91sam9261ek.c;h=d30a1eeef6937463d04544cb7feb82cbd00c1730;hb=bfc325ed38c40c1ecd7f7074720356e464870b0d;hp=14f236da23b8868b95ecc8adec3af9bf3b35ecda;hpb=156feb90d200f186cdfd856d7f6f1878bb1bec1e;p=karo-tx-uboot.git diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 14f236da23..d30a1eeef6 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop + * Stelian Pop * Lead Tech Design * * See file CREDITS for list of people who contributed to this @@ -23,17 +23,20 @@ */ #include +#include #include #include #include +#include #include #include +#include #include -#include #include #include #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) #include +#include #endif DECLARE_GLOBAL_DATA_PTR; @@ -43,106 +46,98 @@ DECLARE_GLOBAL_DATA_PTR; * Miscelaneous platform dependent initialisations */ -static void at91sam9261ek_serial_hw_init(void) -{ -#ifdef CONFIG_USART0 - at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0); -#endif - -#ifdef CONFIG_USART1 - at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1); -#endif - -#ifdef CONFIG_USART2 - at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2); -#endif - -#ifdef CONFIG_USART3 /* DBGU */ - at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); -#endif -} - #ifdef CONFIG_CMD_NAND static void at91sam9261ek_nand_hw_init(void) { + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; unsigned long csa; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | +#ifdef CONFIG_AT91SAM9G10EK + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), + &smc->cs[3].cycle); +#else + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); +#endif + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ - at91_set_gpio_input(AT91_PIN_PC15, 1); + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(AT91_PIN_PC14, 1); + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ } #endif -#ifdef CONFIG_HAS_DATAFLASH -static void at91sam9261ek_spi_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */ - - at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ - at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ - at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ - - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0); -} -#endif - #ifdef CONFIG_DRIVER_DM9000 static void at91sam9261ek_dm9000_hw_init(void) { + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + /* Configure SMC CS2 for DM9000 */ - at91_sys_write(AT91_SMC_SETUP(2), - AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(2), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | - AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); - at91_sys_write(AT91_SMC_CYCLE(2), - AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); - at91_sys_write(AT91_SMC_MODE(2), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | - AT91_SMC_TDF_(1)); +#ifdef CONFIG_AT91SAM9G10EK + writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[2].setup); + writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) | + AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8), + &smc->cs[2].pulse); + writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20), + &smc->cs[2].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[2].mode); +#else + writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[2].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8), + &smc->cs[2].pulse); + writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16), + &smc->cs[2].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[2].mode); +#endif /* Configure Reset signal as output */ at91_set_gpio_output(AT91_PIN_PC10, 0); @@ -167,7 +162,7 @@ vidinfo_t panel_info = { vl_vsync_len: 1, vl_upper_margin:1, vl_lower_margin:0, - mmio: AT91SAM9261_LCDC_BASE, + mmio: ATMEL_BASE_LCDC, }; void lcd_enable(void) @@ -182,6 +177,8 @@ void lcd_disable(void) static void at91sam9261ek_lcd_hw_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ @@ -205,9 +202,12 @@ static void at91sam9261ek_lcd_hw_init(void) at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ - at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); + writel(AT91_PMC_HCK1, &pmc->scer); - gd->fb_base = AT91SAM9261_SRAM_BASE; + /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */ +#ifdef CONFIG_AT91SAM9261EK + gd->fb_base = ATMEL_BASE_SRAM; +#endif } #ifdef CONFIG_LCD_INFO @@ -224,8 +224,8 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", - AT91_CPU_NAME, - strmhz(temp, AT91_CPU_CLOCK)); + ATMEL_CPU_NAME, + strmhz(temp, get_cpu_clk_rate())); dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) @@ -242,20 +242,22 @@ void lcd_show_board_info(void) int board_init(void) { - /* Enable Ctrlc */ - console_init_f(); - +#ifdef CONFIG_AT91SAM9G10EK + /* arch number of AT91SAM9G10EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK; +#else /* arch number of AT91SAM9261EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK; +#endif /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91sam9261ek_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND at91sam9261ek_nand_hw_init(); #endif #ifdef CONFIG_HAS_DATAFLASH - at91sam9261ek_spi_hw_init(); + at91_spi0_hw_init(1 << 0); #endif #ifdef CONFIG_DRIVER_DM9000 at91sam9261ek_dm9000_hw_init(); @@ -266,10 +268,18 @@ int board_init(void) return 0; } +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif + int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; }