X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=board%2Ffreescale%2Fmpc8560ads%2Fmpc8560ads.c;h=423e9d72a761b56b8b024c1190fc832a411a354f;hb=48690d8024eeeaee3120db702e54fcb238e6d9c7;hp=ac7778e25c7c40f87448c5a7947472e480431cfa;hpb=a5d212a263c58cc746481bf1fc878510533ce7d6;p=karo-tx-uboot.git

diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index ac7778e25c..423e9d72a7 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -36,6 +36,7 @@
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <asm/fsl_lbc.h>
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
@@ -235,7 +236,7 @@ void reset_phy (void)
 #endif
 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
 	/* reset PHY */
-	miiphy_reset("FCC1 ETHERNET", 0x0);
+	miiphy_reset("FCC1", 0x0);
 
 	/* change PHY address to 0x02 */
 	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
@@ -321,7 +322,7 @@ void
 local_bus_init(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -380,7 +381,7 @@ local_bus_init(void)
 void
 sdram_init(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	puts("    SDRAM: ");
@@ -389,8 +390,8 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
-	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");