X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=doc%2FREADME.nand;h=0ff56331d5f92ec1ba0dbea186e40d36b4a06cb2;hb=ffcdbd85b18e0e34ce296a4bfa90ec441e9db6c8;hp=487548fcb8ede2e6bd255dfd2021eaf2f1baeaef;hpb=d016dc42cedbf6102e100fa9ecb58462edfb14f8;p=karo-tx-uboot.git

diff --git a/doc/README.nand b/doc/README.nand
index 487548fcb8..0ff56331d5 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -89,18 +89,16 @@ Commands:
 
 Configuration Options:
 
+   CONFIG_SYS_NAND_U_BOOT_OFFS
+	NAND Offset from where SPL will read u-boot image. This is the starting
+	address of u-boot MTD partition in NAND.
+
    CONFIG_CMD_NAND
       Enables NAND support and commmands.
 
    CONFIG_CMD_NAND_TORTURE
       Enables the torture command (see description of this command below).
 
-   CONFIG_MTD_NAND_ECC_JFFS2
-      Define this if you want the Error Correction Code information in
-      the out-of-band data to be formatted to match the JFFS2 file system.
-      CONFIG_MTD_NAND_ECC_YAFFS would be another useful choice for
-      someone to implement.
-
    CONFIG_SYS_MAX_NAND_DEVICE
       The maximum number of NAND devices you want to support.
 
@@ -208,16 +206,88 @@ Platform specific options
 	detection. However ECC calculation on such plaforms would still be
 	done by GPMC controller.
 
+   CONFIG_SPL_NAND_AM33XX_BCH
+	Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
+        hardware ECC correction. This is useful for platforms which have ELM
+	hardware engine and use NAND boot mode.
+	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
+	so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
+        SPL-NAND driver with software ECC correction support.
+
+   CONFIG_NAND_OMAP_ECCSCHEME
+	On OMAP platforms, this CONFIG specifies NAND ECC scheme.
+	It can take following values:
+	OMAP_ECC_HAM1_CODE_SW
+		1-bit Hamming code using software lib.
+		(for legacy devices only)
+	OMAP_ECC_HAM1_CODE_HW
+		1-bit Hamming code using GPMC hardware.
+		(for legacy devices only)
+	OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
+		4-bit BCH code (unsupported)
+	OMAP_ECC_BCH4_CODE_HW
+		4-bit BCH code (unsupported)
+	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+		8-bit BCH code with
+		- ecc calculation using GPMC hardware engine,
+		- error detection using software library.
+		- requires CONFIG_BCH to enable software BCH library
+		(For legacy device which do not have ELM h/w engine)
+	OMAP_ECC_BCH8_CODE_HW
+		8-bit BCH code with
+		- ecc calculation using GPMC hardware engine,
+		- error detection using ELM hardware engine.
+	OMAP_ECC_BCH16_CODE_HW
+		16-bit BCH code with
+		- ecc calculation using GPMC hardware engine,
+		- error detection using ELM hardware engine.
+
+	How to select ECC scheme on OMAP and AMxx platforms ?
+	-----------------------------------------------------
+	Though higher ECC schemes have more capability to detect and correct
+	bit-flips, but still selection of ECC scheme is dependent on following
+	- hardware engines present in SoC.
+		Some legacy OMAP SoC do not have ELM h/w engine thus such
+		SoC cannot support BCHx_HW ECC schemes.
+	- size of OOB/Spare region
+		With higher ECC schemes, more OOB/Spare area is required to
+		store ECC. So choice of ECC scheme is limited by NAND oobsize.
+
+	In general following expression can help:
+		NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
+	where
+		NAND_OOBSIZE	= number of bytes available in
+				OOB/spare area per NAND page.
+		NAND_PAGESIZE	= bytes in main-area of NAND page.
+		ECC_BYTES	= number of ECC bytes generated to
+				protect 512 bytes of data, which is:
+				3 for HAM1_xx ecc schemes
+				7 for BCH4_xx ecc schemes
+				14 for BCH8_xx ecc schemes
+				26 for BCH16_xx ecc schemes
+
+		example to check for BCH16 on 2K page NAND
+		NAND_PAGESIZE = 2048
+		NAND_OOBSIZE = 64
+		2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
+		Thus BCH16 cannot be supported on 2K page NAND.
+
+		However, for 4K pagesize NAND
+		NAND_PAGESIZE = 4096
+		NAND_OOBSIZE = 64
+		ECC_BYTES = 26
+		2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
+		Thus BCH16 can be supported on 4K page NAND.
+
+
+    CONFIG_NAND_OMAP_GPMC_PREFETCH
+	On OMAP platforms that use the GPMC controller
+	(CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
+	uses the prefetch mode to speed up read operations.
 
 NOTE:
 =====
 
-The current NAND implementation is based on what is in recent
-Linux kernels.  The old legacy implementation has been removed.
-
-If you have board code which used CONFIG_NAND_LEGACY, you'll need
-to convert to the current NAND interface for it to continue to work.
-
 The Disk On Chip driver is currently broken and has been for some time.
 There is a driver in drivers/mtd/nand, taken from Linux, that works with
 the current NAND system but has not yet been adapted to the u-boot