X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=drivers%2Fstaging%2Fsm750fb%2Fddk750_display.c;h=f3f0026ac010db1586ff80c4cb8dfd7fa3198691;hb=9bd2c86b5a4d4a038c626d39a02d4dc71ac577ff;hp=84f6e8b8c0e251542cfdd63b8b34a26aa50b6797;hpb=ebd68df3f24b318d391d15c458d6f43f340ba36a;p=karo-tx-linux.git

diff --git a/drivers/staging/sm750fb/ddk750_display.c b/drivers/staging/sm750fb/ddk750_display.c
index 84f6e8b8c0e2..f3f0026ac010 100644
--- a/drivers/staging/sm750fb/ddk750_display.c
+++ b/drivers/staging/sm750fb/ddk750_display.c
@@ -9,35 +9,31 @@
 static void setDisplayControl(int ctrl, int disp_state)
 {
 	/* state != 0 means turn on both timing & plane en_bit */
-	unsigned long ulDisplayCtrlReg, ulReservedBits;
+	unsigned long reg, reserved;
 	int cnt;
 
 	cnt = 0;
 
 	/* Set the primary display control */
 	if (!ctrl) {
-		ulDisplayCtrlReg = PEEK32(PANEL_DISPLAY_CTRL);
+		reg = PEEK32(PANEL_DISPLAY_CTRL);
 		/* Turn on/off the Panel display control */
 		if (disp_state) {
 			/* Timing should be enabled first before enabling the plane
 			 * because changing at the same time does not guarantee that
 			 * the plane will also enabled or disabled.
 			 */
-			ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
-								PANEL_DISPLAY_CTRL, TIMING, ENABLE);
-			POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
+			reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, ENABLE);
+			POKE32(PANEL_DISPLAY_CTRL, reg);
 
-			ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
-								PANEL_DISPLAY_CTRL, PLANE, ENABLE);
+			reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, ENABLE);
 
 			/* Added some masks to mask out the reserved bits.
 			 * Sometimes, the reserved bits are set/reset randomly when
 			 * writing to the PRIMARY_DISPLAY_CTRL, therefore, the register
 			 * reserved bits are needed to be masked out.
 			 */
-			ulReservedBits = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) |
-				FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) |
-				FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE);
+			reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK;
 
 			/* Somehow the register value on the plane is not set
 			 * until a few delay. Need to write
@@ -45,9 +41,9 @@ static void setDisplayControl(int ctrl, int disp_state)
 			 */
 			do {
 				cnt++;
-				POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
-			} while ((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) !=
-					(ulDisplayCtrlReg & ~ulReservedBits));
+				POKE32(PANEL_DISPLAY_CTRL, reg);
+			} while ((PEEK32(PANEL_DISPLAY_CTRL) & ~reserved) !=
+					(reg & ~reserved));
 			printk("Set Panel Plane enbit:after tried %d times\n", cnt);
 		} else {
 			/* When turning off, there is no rule on the programming
@@ -57,46 +53,37 @@ static void setDisplayControl(int ctrl, int disp_state)
 			 * next vertical sync. Need to find out if it is necessary to
 			 * wait for 1 vsync before modifying the timing enable bit.
 			 * */
-			ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
-								PANEL_DISPLAY_CTRL, PLANE, DISABLE);
-			POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
+			reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, DISABLE);
+			POKE32(PANEL_DISPLAY_CTRL, reg);
 
-			ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
-								PANEL_DISPLAY_CTRL, TIMING, DISABLE);
-			POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
+			reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, DISABLE);
+			POKE32(PANEL_DISPLAY_CTRL, reg);
 		}
 
 	} else {
 		/* Set the secondary display control */
-		ulDisplayCtrlReg = PEEK32(CRT_DISPLAY_CTRL);
+		reg = PEEK32(CRT_DISPLAY_CTRL);
 
 		if (disp_state) {
 			/* Timing should be enabled first before enabling the plane because changing at the
 			   same time does not guarantee that the plane will also enabled or disabled.
 			   */
-			ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
-								CRT_DISPLAY_CTRL, TIMING, ENABLE);
-			POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
+			reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, ENABLE);
+			POKE32(CRT_DISPLAY_CTRL, reg);
 
-			ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
-								CRT_DISPLAY_CTRL, PLANE, ENABLE);
+			reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, ENABLE);
 
 			/* Added some masks to mask out the reserved bits.
 			 * Sometimes, the reserved bits are set/reset randomly when
 			 * writing to the PRIMARY_DISPLAY_CTRL, therefore, the register
 			 * reserved bits are needed to be masked out.
 			 */
-
-			ulReservedBits = FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) |
-				FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) |
-				FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE) |
-				FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_4_MASK, ENABLE);
-
+			reserved = CRT_DISPLAY_CTRL_RESERVED_MASK;
 			do {
 				cnt++;
-				POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
-			} while ((PEEK32(CRT_DISPLAY_CTRL) & ~ulReservedBits) !=
-					(ulDisplayCtrlReg & ~ulReservedBits));
+				POKE32(CRT_DISPLAY_CTRL, reg);
+			} while ((PEEK32(CRT_DISPLAY_CTRL) & ~reserved) !=
+					(reg & ~reserved));
 				printk("Set Crt Plane enbit:after tried %d times\n", cnt);
 		} else {
 			/* When turning off, there is no rule on the programming
@@ -106,13 +93,11 @@ static void setDisplayControl(int ctrl, int disp_state)
 			 * vertical sync. Need to find out if it is necessary to
 			 * wait for 1 vsync before modifying the timing enable bit.
 			 */
-			ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
-								CRT_DISPLAY_CTRL, PLANE, DISABLE);
-			POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
+			reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, DISABLE);
+			POKE32(CRT_DISPLAY_CTRL, reg);
 
-			ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
-								CRT_DISPLAY_CTRL, TIMING, DISABLE);
-			POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
+			reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, DISABLE);
+			POKE32(CRT_DISPLAY_CTRL, reg);
 		}
 	}
 }
@@ -126,54 +111,46 @@ static void waitNextVerticalSync(int ctrl, int delay)
 
 		/* Do not wait when the Primary PLL is off or display control is already off.
 		   This will prevent the software to wait forever. */
-		if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PANEL_PLL_CTRL, POWER) ==
-			 PANEL_PLL_CTRL_POWER_OFF) ||
-			(FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) ==
-			 PANEL_DISPLAY_CTRL_TIMING_DISABLE)) {
+		if (!(PEEK32(PANEL_PLL_CTRL) & PLL_CTRL_POWER) ||
+			(FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL),
+				DISPLAY_CTRL, TIMING) ==
+				DISPLAY_CTRL_TIMING_DISABLE)) {
 			return;
 		}
 
 		while (delay-- > 0) {
 			/* Wait for end of vsync. */
 			do {
-				status = FIELD_GET(PEEK32(SYSTEM_CTRL),
-						   SYSTEM_CTRL,
-						   PANEL_VSYNC);
-			} while (status == SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
+				status = PEEK32(SYSTEM_CTRL);
+			} while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
 
 			/* Wait for start of vsync. */
 			do {
-				status = FIELD_GET(PEEK32(SYSTEM_CTRL),
-						   SYSTEM_CTRL,
-						   PANEL_VSYNC);
-			} while (status == SYSTEM_CTRL_PANEL_VSYNC_INACTIVE);
+				status = PEEK32(SYSTEM_CTRL);
+			} while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));
 		}
 
 	} else {
 
 		/* Do not wait when the Primary PLL is off or display control is already off.
 			   This will prevent the software to wait forever. */
-		if ((FIELD_GET(PEEK32(CRT_PLL_CTRL), CRT_PLL_CTRL, POWER) ==
-			 CRT_PLL_CTRL_POWER_OFF) ||
-			(FIELD_GET(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, TIMING) ==
-			 CRT_DISPLAY_CTRL_TIMING_DISABLE)) {
+		if (!(PEEK32(CRT_PLL_CTRL) & PLL_CTRL_POWER) ||
+			(FIELD_GET(PEEK32(CRT_DISPLAY_CTRL),
+				DISPLAY_CTRL, TIMING) ==
+				DISPLAY_CTRL_TIMING_DISABLE)) {
 			return;
 		}
 
 		while (delay-- > 0) {
 			/* Wait for end of vsync. */
 			do {
-				status = FIELD_GET(PEEK32(SYSTEM_CTRL),
-								   SYSTEM_CTRL,
-								   CRT_VSYNC);
-			} while (status == SYSTEM_CTRL_CRT_VSYNC_ACTIVE);
+				status = PEEK32(SYSTEM_CTRL);
+			} while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
 
 			/* Wait for start of vsync. */
 			do {
-				status = FIELD_GET(PEEK32(SYSTEM_CTRL),
-								   SYSTEM_CTRL,
-								   CRT_VSYNC);
-			} while (status == SYSTEM_CTRL_CRT_VSYNC_INACTIVE);
+				status = PEEK32(SYSTEM_CTRL);
+			} while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));
 		}
 	}
 }