X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=include%2Fconfigs%2FHIDDEN_DRAGON.h;h=ddeccb08686e0e197aaeab6b70bfb859bd994102;hb=3b7891f1498f77e7df66b7955accb946e9eb6037;hp=26dd954c18a7eff11f31506475feed5f11d7f0f5;hpb=6bf6f114dcdd97ec3f80c2761ed40e31229d6b78;p=karo-tx-uboot.git diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h index 26dd954c18..ddeccb0868 100644 --- a/include/configs/HIDDEN_DRAGON.h +++ b/include/configs/HIDDEN_DRAGON.h @@ -5,23 +5,7 @@ * (C) Copyright 2001, 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* ------------------------------------------------------------------------- */ @@ -42,6 +26,8 @@ #define CONFIG_MPC8245 1 #define CONFIG_HIDDEN_DRAGON 1 +#define CONFIG_SYS_TEXT_BASE 0xFFF00000 + #if 0 #define USE_DINK32 1 #else @@ -77,25 +63,25 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP 1 /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- */ #define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #undef CONFIG_PCI_PNP -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define PCI_ENET0_IOADDR 0x80000000 #define PCI_ENET0_MEMADDR 0x80000000 @@ -103,9 +89,7 @@ #define PCI_ENET1_MEMADDR 0x81000000 #define CONFIG_RTL8139 -#define _IO_BASE 0x00000000 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) + /* Make sure the ethaddr can be overwritten TODO: Remove this on final product */ @@ -114,53 +98,51 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x02000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_MAX_RAM_SIZE 0x02000000 -#define CFG_RESET_ADDRESS 0xFFF00100 +#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 #if defined (USE_DINK32) -#define CFG_MONITOR_LEN 0x00030000 -#define CFG_MONITOR_BASE 0x00090000 -#define CFG_RAMBOOT 1 -#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_INIT_RAM_END 0x10000 -#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_MONITOR_LEN 0x00030000 +#define CONFIG_SYS_MONITOR_BASE 0x00090000 +#define CONFIG_SYS_RAMBOOT 1 +#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #else -#undef CFG_RAMBOOT -#define CFG_MONITOR_LEN 0x00030000 -#define CFG_MONITOR_BASE TEXT_BASE +#undef CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_MONITOR_LEN 0x00030000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CFG_GBL_DATA_SIZE 128 -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #endif -#define CFG_FLASH_BASE 0xFFE00000 -#define CFG_FLASH_SIZE (2 * 1024 * 1024) /* Unity has onboard 1MByte flash */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ +#define CONFIG_SYS_FLASH_BASE 0xFFE00000 +#define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* Unity has onboard 1MByte flash */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ +#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ -#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ -#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ -#define CFG_EUMB_ADDR 0xFC000000 +#define CONFIG_SYS_EUMB_ADDR 0xFC000000 -#define CFG_ISA_MEM 0xFD000000 -#define CFG_ISA_IO 0xFE000000 +#define CONFIG_SYS_ISA_MEM 0xFD000000 +#define CONFIG_SYS_ISA_IO 0xFE000000 -#define CFG_FLASH_RANGE_BASE 0xFFE00000 /* flash memory address range */ -#define CFG_FLASH_RANGE_SIZE 0x00200000 +#define CONFIG_SYS_FLASH_RANGE_BASE 0xFFE00000 /* flash memory address range */ +#define CONFIG_SYS_FLASH_RANGE_SIZE 0x00200000 #define FLASH_BASE0_PRELIM 0xFFE00000 /* processor board flash */ /* @@ -171,12 +153,15 @@ * configuration items that the driver uses to drive the port pins. */ #define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F +#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F -#ifdef CONFIG_SOFT_I2C +#ifdef CONFIG_SYS_I2C_SOFT #error "Soft I2C is not configured properly. Please review!" +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SOFT_SPEED 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ #define I2C_ACTIVE (iop->pdir |= 0x00010000) #define I2C_TRISTATE (iop->pdir &= ~0x00010000) @@ -186,70 +171,69 @@ #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ else iop->pdat &= ~0x00020000 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif /* CONFIG_SOFT_I2C */ +#endif /* CONFIG_SYS_I2C_SOFT */ -#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM } +#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM } /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_WINBOND_83C553 1 /*has a winbond bridge */ -#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ -#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ -#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ +/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */ +#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ +#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ +#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ +#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ +#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ /* TODO: Change this to VIA686A */ /* * NS87308 Configuration */ -#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */ +#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ -#define CFG_NS87308_BADDR_10 1 +#define CONFIG_SYS_NS87308_BADDR_10 1 -#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \ - CFG_NS87308_UART2 | \ - CFG_NS87308_POWRMAN | \ - CFG_NS87308_RTC_APC ) +#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \ + CONFIG_SYS_NS87308_UART2 | \ + CONFIG_SYS_NS87308_POWRMAN | \ + CONFIG_SYS_NS87308_RTC_APC ) -#undef CFG_NS87308_PS2MOD +#undef CONFIG_SYS_NS87308_PS2MOD -#define CFG_NS87308_CS0_BASE 0x0076 -#define CFG_NS87308_CS0_CONF 0x30 -#define CFG_NS87308_CS1_BASE 0x0075 -#define CFG_NS87308_CS1_CONF 0x30 -#define CFG_NS87308_CS2_BASE 0x0074 -#define CFG_NS87308_CS2_CONF 0x30 +#define CONFIG_SYS_NS87308_CS0_BASE 0x0076 +#define CONFIG_SYS_NS87308_CS0_CONF 0x30 +#define CONFIG_SYS_NS87308_CS1_BASE 0x0075 +#define CONFIG_SYS_NS87308_CS1_CONF 0x30 +#define CONFIG_SYS_NS87308_CS2_BASE 0x0074 +#define CONFIG_SYS_NS87308_CS2_CONF 0x30 /* * NS16550 Configuration */ -#define CFG_NS16550 -#define CFG_NS16550_SERIAL +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_REG_SIZE 1 #if (CONFIG_CONS_INDEX > 2) -#define CFG_NS16550_CLK CONFIG_DRAM_SPEED*1000000 +#define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000 #else -#define CFG_NS16550_CLK 1843200 +#define CONFIG_SYS_NS16550_CLK 1843200 #endif -#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE) -#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE) -#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4500) -#define CFG_NS16550_COM4 (CFG_EUMB_ADDR + 0x4600) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600) /* * Low Level Configuration Settings @@ -259,27 +243,27 @@ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CFG_ROMNAL 7 /*rom/flash next access time */ -#define CFG_ROMFAL 11 /*rom/flash access time */ +#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ +#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ -#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */ +#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */ /* the following are for SDRAM only*/ -#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ -#define CFG_REFREC 8 /* Refresh to activate interval */ -#define CFG_RDLAT 4 /* data latency from read command */ -#define CFG_PRETOACT 3 /* Precharge to activate interval */ -#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ -#define CFG_ACTORW 3 /* Activate to R/W */ -#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ -#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ +#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ +#define CONFIG_SYS_RDLAT 4 /* data latency from read command */ +#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ +#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ +#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ +#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ #if 0 -#define CFG_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ +#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ #endif -#define CFG_REGISTERD_TYPE_BUFFER 1 -#define CFG_EXTROM 1 -#define CFG_REGDIMM 0 +#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 +#define CONFIG_SYS_EXTROM 1 +#define CONFIG_SYS_REGDIMM 0 /* memory bank settings*/ @@ -289,103 +273,95 @@ * bits will be set to 0x00000 for a start address, or 0xfffff for an * end address */ -#define CFG_BANK0_START 0x00000000 -#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) -#define CFG_BANK0_ENABLE 1 -#define CFG_BANK1_START 0x3ff00000 -#define CFG_BANK1_END 0x3fffffff -#define CFG_BANK1_ENABLE 0 -#define CFG_BANK2_START 0x3ff00000 -#define CFG_BANK2_END 0x3fffffff -#define CFG_BANK2_ENABLE 0 -#define CFG_BANK3_START 0x3ff00000 -#define CFG_BANK3_END 0x3fffffff -#define CFG_BANK3_ENABLE 0 -#define CFG_BANK4_START 0x00000000 -#define CFG_BANK4_END 0x00000000 -#define CFG_BANK4_ENABLE 0 -#define CFG_BANK5_START 0x00000000 -#define CFG_BANK5_END 0x00000000 -#define CFG_BANK5_ENABLE 0 -#define CFG_BANK6_START 0x00000000 -#define CFG_BANK6_END 0x00000000 -#define CFG_BANK6_ENABLE 0 -#define CFG_BANK7_START 0x00000000 -#define CFG_BANK7_END 0x00000000 -#define CFG_BANK7_ENABLE 0 +#define CONFIG_SYS_BANK0_START 0x00000000 +#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) +#define CONFIG_SYS_BANK0_ENABLE 1 +#define CONFIG_SYS_BANK1_START 0x3ff00000 +#define CONFIG_SYS_BANK1_END 0x3fffffff +#define CONFIG_SYS_BANK1_ENABLE 0 +#define CONFIG_SYS_BANK2_START 0x3ff00000 +#define CONFIG_SYS_BANK2_END 0x3fffffff +#define CONFIG_SYS_BANK2_ENABLE 0 +#define CONFIG_SYS_BANK3_START 0x3ff00000 +#define CONFIG_SYS_BANK3_END 0x3fffffff +#define CONFIG_SYS_BANK3_ENABLE 0 +#define CONFIG_SYS_BANK4_START 0x00000000 +#define CONFIG_SYS_BANK4_END 0x00000000 +#define CONFIG_SYS_BANK4_ENABLE 0 +#define CONFIG_SYS_BANK5_START 0x00000000 +#define CONFIG_SYS_BANK5_END 0x00000000 +#define CONFIG_SYS_BANK5_ENABLE 0 +#define CONFIG_SYS_BANK6_START 0x00000000 +#define CONFIG_SYS_BANK6_END 0x00000000 +#define CONFIG_SYS_BANK6_ENABLE 0 +#define CONFIG_SYS_BANK7_START 0x00000000 +#define CONFIG_SYS_BANK7_END 0x00000000 +#define CONFIG_SYS_BANK7_ENABLE 0 /* * Memory bank enable bitmask, specifying which of the banks defined above are actually present. MSB is for bank #7, LSB is for bank #0. */ -#define CFG_BANK_ENABLE 0x01 +#define CONFIG_SYS_BANK_ENABLE 0x01 -#define CFG_ODCR 0xff /* configures line driver impedances, */ +#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ /* see 8240 book for bit definitions */ -#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ +#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ /* currently accessed page in memory */ /* see 8240 book for details */ /* SDRAM 0 - 256MB */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) /* stack in DCACHE @ 1GB (no backing mem) */ #if defined(USE_DINK32) -#define CFG_IBAT1L (0x40000000 | BATL_PP_00 ) -#define CFG_IBAT1U (0x40000000 | BATU_BL_128K ) +#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) +#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) #else -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) #endif /* PCI memory */ -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) /* Flash, config addrs, etc */ -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U +#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 36 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 36 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ #if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - /* values according to the manual */ #define CONFIG_DRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ