X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=include%2Fconfigs%2Fhermes.h;h=736ffb613dced6daad713b8133b8be8cb1de40d1;hb=0e1612a7d1578217f89bd55ac2c0d582e2f44c0f;hp=91117bab726242f00eeb9a5253e86dca829bc46b;hpb=fe126d8b34d2e7c3c2dc1d4e61086018e016768c;p=karo-tx-uboot.git diff --git a/include/configs/hermes.h b/include/configs/hermes.h index 91117bab72..736ffb613d 100644 --- a/include/configs/hermes.h +++ b/include/configs/hermes.h @@ -2,23 +2,7 @@ * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -36,6 +20,8 @@ #define CONFIG_MPC860 1 /* This is a MPC860T CPU */ #define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */ +#define CONFIG_SYS_TEXT_BASE 0xFE000000 + #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE @@ -54,53 +40,53 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_COMMANDS CONFIG_CMD_DFL -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/* + * Command line configuration. + */ +#include -/*----------------------------------------------------------------------*/ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH -/*----------------------------------------------------------------------*/ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ -#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ +#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_ALLOC_DPRAM 1 /* use allocation routines */ +#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */ /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) @@ -109,56 +95,55 @@ /*----------------------------------------------------------------------- * Internal Memory Mapped Register */ -#define CFG_IMMR 0xFF000000 /* Non-Standard value! */ +#define CONFIG_SYS_IMMR 0xFF000000 /* Non-Standard value! */ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR +#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFE000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE 0xFE000000 #ifdef DEBUG -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #else -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ #endif -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 124 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */ +#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif /*----------------------------------------------------------------------- @@ -169,10 +154,10 @@ * +0x0004 */ #if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ +#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) #endif /*----------------------------------------------------------------------- @@ -180,7 +165,7 @@ *----------------------------------------------------------------------- * +0x0000 => 0x000000C0 */ -#define CFG_SIUMCR 0 +#define CONFIG_SYS_SIUMCR 0 /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control 11-26 @@ -188,7 +173,7 @@ * Clear Reference Interrupt Status, Timebase freezing enabled * +0x0200 => 0x00C2 */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) +#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 @@ -196,7 +181,7 @@ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled * +0x0240 => 0x0082 */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) +#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 @@ -205,7 +190,7 @@ * interrupt status bit, set PLL multiplication factor ! */ /* +0x0286 => 0x00B0D0C0 */ -#define CFG_PLPRCR \ +#define CONFIG_SYS_PLPRCR \ ( (11 << PLPRCR_MF_SHIFT) | \ PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ @@ -220,9 +205,9 @@ */ #define SCCR_MASK SCCR_EBDF11 /* +0x0282 => 0x03800000 */ -#define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \ +#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS | \ SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ SCCR_EBDF00 | SCCR_DFSYNC00 | \ SCCR_DFBRG00 | SCCR_DFNL000 | \ SCCR_DFNH000) @@ -232,7 +217,7 @@ *----------------------------------------------------------------------- */ /* +0x0220 => 0x00C3 */ -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) +#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) /*----------------------------------------------------------------------- @@ -240,20 +225,20 @@ *----------------------------------------------------------------------- */ /* +0x09C4 => TIMEP=1 */ -#define CFG_RCCR 0x0100 +#define CONFIG_SYS_RCCR 0x0100 /*----------------------------------------------------------------------- * RMDS - RISC Microcode Development Support Control Register *----------------------------------------------------------------------- */ -#define CFG_RMDS 0 +#define CONFIG_SYS_RMDS 0 /*----------------------------------------------------------------------- * *----------------------------------------------------------------------- * */ -#define CFG_DER 0 +#define CONFIG_SYS_DER 0 /* * Init Memory Controller: @@ -268,17 +253,17 @@ * but not too much to meddle with FLASH accesses */ /* allow for max 4 MB of Flash */ -#define CFG_REMAP_OR_AM 0xFFC00000 /* OR addr mask */ -#define CFG_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */ +#define CONFIG_SYS_REMAP_OR_AM 0xFFC00000 /* OR addr mask */ +#define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */ /* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \ +#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \ OR_SCY_5_CLK | OR_TRLX) -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) +#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 8 bit, bank valid */ -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) +#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) /* * BR1/OR1 - SDRAM @@ -291,8 +276,8 @@ #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ -#define CFG_OR1_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#define CONFIG_SYS_OR1_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) +#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) /* * BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide @@ -301,8 +286,8 @@ #define HPRO2_OR_AM 0xFFFF8000 #define HPRO2_TIMING 0x00000934 -#define CFG_OR2 (HPRO2_OR_AM | HPRO2_TIMING) -#define CFG_BR2 ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) +#define CONFIG_SYS_OR2 (HPRO2_OR_AM | HPRO2_TIMING) +#define CONFIG_SYS_BR2 ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) /* * BR3/OR3: not used @@ -317,23 +302,14 @@ */ /* periodic timer for refresh */ -#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ +#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ /* 8 column SDRAM */ -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ +#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) /* 9 column SDRAM */ -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ +#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - #endif /* __CONFIG_H */