X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=include%2Fconfigs%2Fiocon.h;h=38d473de4298503ba5fe53d7a36a5ffefaa2b618;hb=d9f923ffcb60be6817cff37c76e21faede8d2819;hp=ec9016a6d14b89ffa2444d4e725a11965658448f;hpb=31043e20ae748635f142483e8b7b645948687055;p=karo-tx-uboot.git

diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index ec9016a6d1..38d473de42 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -2,14 +2,13 @@
  * (C) Copyright 2010
  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
  *
- * SPDX-License-Identifier:	GPL-2.0+ 
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #define CONFIG_405EP		1	/* this is a PPC405 CPU */
-#define CONFIG_4xx		1	/*  member of PPC4xx family */
 #define CONFIG_IOCON		1	/*  on a IoCon board */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
@@ -18,12 +17,13 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAME		iocon
-#define CONFIG_IDENT_STRING	" iocon 0.05"
+#define CONFIG_IDENT_STRING	" iocon 0.06"
 #include "amcc-common.h"
 
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_LAST_STAGE_INIT
+#define CONFIG_SYS_GENERIC_BOARD
 
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
 
@@ -40,6 +40,7 @@
 /* new uImage format support */
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
 
 #define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
 
@@ -65,6 +66,10 @@
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_FPGAD
 #undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_NFS
 
 /*
  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
@@ -100,12 +105,27 @@
 #define CONFIG_SYS_I2C_PPC4XX_CH0
 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+#define CONFIG_SYS_I2C_IHS
 
 #define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_SPD_BUS_NUM		4
 
 #define CONFIG_PCA953X			/* NXP PCA9554 */
 #define CONFIG_PCA9698			/* NXP PCA9698 */
 
+#define CONFIG_SYS_I2C_IHS_CH0
+#define CONFIG_SYS_I2C_IHS_SPEED_0		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0		0x7F
+#define CONFIG_SYS_I2C_IHS_CH1
+#define CONFIG_SYS_I2C_IHS_SPEED_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH2
+#define CONFIG_SYS_I2C_IHS_SPEED_2		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2		0x7F
+#define CONFIG_SYS_I2C_IHS_CH3
+#define CONFIG_SYS_I2C_IHS_SPEED_3		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3		0x7F
+
 /*
  * Software (bit-bang) I2C driver configuration
  */
@@ -122,7 +142,9 @@
 #define CONFIG_SYS_I2C_SOFT_SPEED_4		50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F
 
-#define CONFIG_SYS_CH7301_I2C			{1, 2, 3, 4}
+#define CONFIG_SYS_ICS8N3QV01_I2C		{5, 6, 7, 8}
+#define CONFIG_SYS_CH7301_I2C			{5, 6, 7, 8}
+#define CONFIG_SYS_DP501_I2C			{0, 1, 2, 3}
 
 #ifndef __ASSEMBLY__
 void fpga_gpio_set(unsigned int bus, int pin);
@@ -150,12 +172,6 @@ int fpga_gpio_get(unsigned int bus, int pin);
 	} while (0)
 #define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */
 
-/*
- * OSD hardware
- */
-#define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_CH7301
-
 /*
  * FLASH organization
  */
@@ -239,9 +255,8 @@ int fpga_gpio_get(unsigned int bus, int pin);
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 #define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size/bytes res'd for init data*/
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -285,8 +300,9 @@ int fpga_gpio_get(unsigned int bus, int pin);
  * OSD Setup
  */
 #define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_CH7301
 #define CONFIG_SYS_OSD_SCREENS		1
+#define CONFIG_SYS_DP501_DIFFERENTIAL
+#define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */
 
 #define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
 #define CONFIG_BITBANGMII_MULTI