X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=include%2Fconfigs%2Fkilauea.h;h=1990b2df15030aab6789d60519b3eea848091954;hb=0bfcc924552b8ec79a20b8b12557ff08742c4f0e;hp=48dc9463a8d20c762be5d0289a9dab3bb092668f;hpb=500fbae2043532275e09a8666d837d052c9bad9a;p=karo-tx-uboot.git diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 48dc9463a8..1990b2df15 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -5,23 +5,7 @@ * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /************************************************************************ @@ -35,10 +19,27 @@ * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_KILAUEA 1 /* Board is Kilauea */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_405EX 1 /* Specifc 405EX support*/ #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 +#endif + +/* + * CHIP_21 errata - you must set this to match your exact CPU, else your + * board will not boot. DO NOT enable this unless you have JTAG available + * for recovery, in the event you get it wrong. + * + * Kilauea uses the 405EX, while Haleakala uses the 405EXr. Either board + * may be equipped for security or not. You must look at the CPU part + * number to be sure what you have. + */ +/* #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY */ +/* #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY */ +/* #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY */ +/* #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY */ + /* * Include common defines/options for all AMCC eval boards */ @@ -57,7 +58,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFC000000 #define CONFIG_SYS_NAND_ADDR 0xF8000000 #define CONFIG_SYS_FPGA_BASE 0xF0000000 -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ /*----------------------------------------------------------------------- * Initial RAM & Stack Pointer Configuration Options @@ -89,9 +89,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */ #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ -#define CONFIG_SYS_INIT_RAM_END (4 << 10) /* 4 KiB */ -#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) /* 4 KiB */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * If the data cache is being used for the primordial stack and global @@ -103,11 +102,10 @@ #if defined(CONFIG_SYS_INIT_DCACHE_CS) # define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -# define CONFIG_SYS_POST_ALT_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) +# define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) #else # define CONFIG_SYS_INIT_EXTRA_SIZE 16 # define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE) -# define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 4) # define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ @@ -115,18 +113,12 @@ * Serial Port *----------------------------------------------------------------------*/ #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ -/* define this if you want console on UART1 */ -#undef CONFIG_UART1_CONSOLE +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ -#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ -#endif /*----------------------------------------------------------------------- * FLASH related @@ -154,63 +146,6 @@ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif /* CONFIG_ENV_IS_IN_FLASH */ -/* - * IPL (Initial Program Loader, integrated inside CPU) - * Will load first 4k from NAND (SPL) into cache and execute it from there. - * - * SPL (Secondary Program Loader) - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL - * has to fit into 4kByte. It sets up the CPU and configures the SDRAM - * controller and the NAND controller so that the special U-Boot image can be - * loaded from NAND to SDRAM. - * - * NUB (NAND U-Boot) - * This NAND U-Boot (NUB) is a special U-Boot version which can be started - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. - * - * On 405EX the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from location 0xfffff000...0xffffffff the - * NAND controller cannot be accessed since it is attached to CS0 too. - */ -#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ -#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */ -#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) - -/* - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) - */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ - -/* - * Now the NAND chip has to be defined (no autodetection used!) - */ -#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ -#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ -#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */ - -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE) -#define CONFIG_SYS_NAND_OOBSIZE 16 -#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS) -#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} - -#ifdef CONFIG_ENV_IS_IN_NAND -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/sequoia/u-boot-nand.lds for details. - */ -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#endif - /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ @@ -235,11 +170,9 @@ * * DDR Autocalibration Method_B is the default. */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ #undef CONFIG_PPC4xx_DDR_METHOD_A -#endif #define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE) @@ -373,7 +306,7 @@ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ @@ -421,7 +354,6 @@ CONFIG_AMCC_DEF_ENV_POWERPC \ CONFIG_AMCC_DEF_ENV_PPC_OLD \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ - CONFIG_AMCC_DEF_ENV_NAND_UPD \ "logversion=2\0" \ "kernel_addr=fc000000\0" \ "fdt_addr=fc1e0000\0" \ @@ -435,21 +367,11 @@ */ #define CONFIG_CMD_CHIP_CONFIG #define CONFIG_CMD_DATE -#define CONFIG_CMD_LOG #define CONFIG_CMD_NAND #define CONFIG_CMD_PCI #define CONFIG_CMD_SNTP -/* - * Don't run the memory POST on the NAND-booting version. It will - * overwrite part of the U-Boot image which is already loaded from NAND - * to SDRAM. - */ -#if defined(CONFIG_NAND_U_BOOT) -#define CONFIG_SYS_POST_MEMORY_ON 0 -#else #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY -#endif /* POST support */ #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ @@ -460,7 +382,8 @@ CONFIG_SYS_POST_UART) /* Define here the base-addresses of the UARTs to test in POST */ -#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE, UART1_BASE} +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ + CONFIG_SYS_NS16550_COM2 } #define CONFIG_LOGBUFFER #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ @@ -471,6 +394,7 @@ * PCI stuff *----------------------------------------------------------------------*/ #define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ #define CONFIG_PCI_CONFIG_HOST_BRIDGE @@ -498,18 +422,6 @@ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) -/* booting from NAND, so NAND chips select has to be on CS 0 */ -#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ - -/* Memory Bank 1 (NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x05806500 -#define CONFIG_SYS_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/ - -/* Memory Bank 0 (NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x018003c0 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1e000) -#else #define CONFIG_SYS_NAND_CS 1 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ @@ -519,7 +431,6 @@ /* Memory Bank 1 (NAND-FLASH) initialization */ #define CONFIG_SYS_EBC_PB1AP 0x018003c0 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_ADDR | 0x1e000) -#endif /* Memory Bank 2 (FPGA) initialization */ #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_ENABLED | \