X-Git-Url: https://git.kernelconcepts.de/?a=blobdiff_plain;f=include%2Fmpc86xx.h;h=eb85d60cad1bfa3688d70adbaa446a44e0497b6c;hb=6d2231e8fa21f4bc4fcff3690146540f30984d61;hp=673bfed16e9832054835420e7e7d3ff4f5f3be53;hpb=f3679aa13d9f483adb38245a87ecd5c84f57a5d3;p=karo-tx-uboot.git diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 673bfed16e..eb85d60cad 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -7,16 +7,18 @@ #ifndef __MPC86xx_H__ #define __MPC86xx_H__ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ +#include +#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ +#define _START_OFFSET EXC_OFF_SYS_RESET /* * platform register addresses */ -#define GUTS_SVR (CFG_CCSRBAR + 0xE00A4) -#define MCM_ABCR (CFG_CCSRBAR + 0x01000) -#define MCM_DBCR (CFG_CCSRBAR + 0x01008) +#define GUTS_SVR (CONFIG_SYS_CCSRBAR + 0xE00A4) +#define MCM_ABCR (CONFIG_SYS_CCSRBAR + 0x01000) +#define MCM_DBCR (CONFIG_SYS_CCSRBAR + 0x01008) /* * l2cr values. Look in config_.h for the actual setup @@ -32,47 +34,6 @@ #define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ #define L2CR_L2IP 0x00000001 /* global invalidate in progress */ -/* - * BAT settings. Look in config_.h for the actual setup - */ - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc -#define BATU_BL_512M 0x00003ffc -#define BATU_BL_1G 0x00007ffc -#define BATU_BL_2G 0x0000fffc -#define BATU_BL_4G 0x0001fffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 -#define BATU_INVALID 0x00000000 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 -#define BATL_NO_ACCESS 0x00000000 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - -#define BATL_PP_NO_ACCESS BATL_PP_00 -#define BATL_PP_RO BATL_PP_01 -#define BATL_PP_RW BATL_PP_10 - #define HID0_XBSEN 0x00000100 #define HID0_HIGH_BAT_EN 0x00800000 #define HID0_XAEN 0x00020000 @@ -82,6 +43,7 @@ typedef struct { unsigned long freqProcessor; unsigned long freqSystemBus; + unsigned long freqLocalBus; } MPC86xx_SYS_INFO; #define l1icache_enable icache_enable @@ -121,5 +83,7 @@ static __inline__ unsigned long get_l2cr (void) return l2cr_val; } +void setup_ddr_bat(phys_addr_t dram_size); + #endif /* _ASMLANGUAGE */ #endif /* __MPC86xx_H__ */