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ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level
authorGregory CLEMENT <gregory.clement@free-electrons.com>
Tue, 17 Mar 2015 16:33:54 +0000 (17:33 +0100)
committerGregory CLEMENT <gregory.clement@free-electrons.com>
Thu, 19 Mar 2015 10:07:47 +0000 (11:07 +0100)
commit292a3546b9eb20bf5a292f4e55dd1a027424669f
tree86a3651ede92225bbbbd6e6819263b584efde379tree | snapshot
parentb7f01842bcbbf8aaf26c9f9bd413774114fa83c9commit | diff
ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level

For L2 cache controller node, cache-level property is mandatory. Let's
add it to Armada 370 and Armada XP device tree.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
arch/arm/boot/dts/armada-370.dtsi diff | blob | history
arch/arm/boot/dts/armada-xp.dtsi diff | blob | history
Linux kernel for KaRo TX COM modules