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ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1
authorMarek Vasut <marex@denx.de>
Tue, 21 Jul 2015 03:00:42 +0000 (05:00 +0200)
committerMarek Vasut <marex@denx.de>
Sat, 8 Aug 2015 12:14:22 +0000 (14:14 +0200)
commit3b44f55c3b9ecc570cde507a826245974bf11af6
tree1b4a1bde7775e60028821f91fa250dd5fb2bdefftree | snapshot
parentac63b9ada5c9dd88f0dfdc9a3f027d3b3a8c31e2commit | diff
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1

Fix data types and constify where applicable, fix broken multiline
debug strings and fix comments. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
drivers/ddr/altera/sequencer.c diff | blob | history
UBoot for KaRo TX COM modules