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(parent: 6b85aae) | patch
agp/intel: Fix cache control for Sandybridge
authorZhenyu Wang <zhenyuw@linux.intel.com>
Fri, 27 Aug 2010 03:08:57 +0000 (11:08 +0800)
committerGreg Kroah-Hartman <gregkh@suse.de>
Fri, 29 Oct 2010 04:51:44 +0000 (21:51 -0700)
commitc4cf17f1e6a95168d479656d066c5b8324c16b06
tree74ce6f9d1207da5b4b0712f278d3bd7495d947b8tree | snapshot
parent6b85aae5dfa34321a2336f57109cd9ad4ae1bb51commit | diff
agp/intel: Fix cache control for Sandybridge

commit f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337 upstream.

Sandybridge GTT has new cache control bits in PTE, which controls
graphics page cache in LLC or LLC/MLC, so we need to extend the mask
function to respect the new bits.

And set cache control to always LLC only by default on Gen6.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
drivers/char/agp/intel-agp.c diff | blob | history
drivers/char/agp/intel-agp.h diff | blob | history
drivers/char/agp/intel-gtt.c diff | blob | history
drivers/gpu/drm/i915/i915_gem.c diff | blob | history
include/linux/intel-gtt.h [new file with mode: 0644] blob
Linux kernel for KaRo TX COM modules