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powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL
authorPrabhakar Kushwaha <prabhakar@freescale.com>
Tue, 7 May 2013 05:49:55 +0000 (11:19 +0530)
committerAndy Fleming <afleming@freescale.com>
Thu, 20 Jun 2013 22:08:47 +0000 (17:08 -0500)
commitf64bd7c038468de7b6cfa47e88dd0f5ce6c38504
tree89bb895f51f24167e88ecdb7a96b8f5dbd4df519tree | snapshot
parent8bd00c9494a19ef4ea2a0a9aa695ff111a380850commit | diff
powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL

e500v2 processor does not support 8K page size TLB entries.

So create new TLB entry only during NAND SPL boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
board/freescale/bsc9131rdb/tlb.c diff | blob | history
board/freescale/bsc9132qds/tlb.c diff | blob | history
board/freescale/p1010rdb/tlb.c diff | blob | history
UBoot for KaRo TX COM modules