Some GPIO line limits are incorrectly set which, for instance,
does not allow nRTS1 (GPH11) configuration on a S3C2416 chip.
Signed-off-by: José Miguel Gonçalves <jose.goncalves@inov.pt>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
.base = S3C2410_GPA(0),
.owner = THIS_MODULE,
.label = "GPIOA",
.base = S3C2410_GPA(0),
.owner = THIS_MODULE,
.label = "GPIOA",
.direction_input = s3c24xx_gpiolib_banka_input,
.direction_output = s3c24xx_gpiolib_banka_output,
},
.direction_input = s3c24xx_gpiolib_banka_input,
.direction_output = s3c24xx_gpiolib_banka_output,
},
.base = S3C2410_GPB(0),
.owner = THIS_MODULE,
.label = "GPIOB",
.base = S3C2410_GPB(0),
.owner = THIS_MODULE,
.label = "GPIOB",
.base = S3C2410_GPH(0),
.owner = THIS_MODULE,
.label = "GPIOH",
.base = S3C2410_GPH(0),
.owner = THIS_MODULE,
.label = "GPIOH",
},
},
/* GPIOS for the S3C2443 and later devices. */
},
},
/* GPIOS for the S3C2443 and later devices. */
* 2410 2412 2440 2443 2416
* 2442
* ---- ---- ---- ---- ----
* 2410 2412 2440 2443 2416
* 2442
* ---- ---- ---- ---- ----
- * A 23 22 25 16 25
- * B 11 11 11 11 9
- * C 16 15 16 16 16
+ * A 23 22 25 16 27
+ * B 11 11 11 11 11
+ * C 16 16 16 16 16
* D 16 16 16 16 16
* E 16 16 16 16 16
* F 8 8 8 8 8
* G 16 16 16 16 8
* D 16 16 16 16 16
* E 16 16 16 16 16
* F 8 8 8 8 8
* G 16 16 16 16 8
* J -- -- 13 16 --
* K -- -- -- -- 16
* J -- -- 13 16 --
* K -- -- -- -- 16