irqchip/ath79-misc: Move the MISC driver from arch/mips/ath79/

The driver stays the same but the initialization changes a bit.
For OF boards we now get the memory map from the OF node and use
a linear mapping instead of the legacy mapping. For legacy boards
we still use a legacy mapping and just pass down all the parameters
from the board init code.

Signed-off-by: Alban Bedel <albeu@free.fr>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1453553867-27003-1-git-send-email-albeu@free.fr
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index 511c06560dc1f5a95866f832ec9ae2180048b9d5..05b45140bc1fe79616482f0996be0c1722debc5f 100644 (file)
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -26,90 +26,6 @@
 #include "common.h"
 #include "machtypes.h"
 
-static void __init ath79_misc_intc_domain_init(
-       struct device_node *node, int irq);
-
-static void ath79_misc_irq_handler(struct irq_desc *desc)
-{
-       struct irq_domain *domain = irq_desc_get_handler_data(desc);
-       void __iomem *base = domain->host_data;
-       u32 pending;
-
-       pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
-                 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
-
-       if (!pending) {
-               spurious_interrupt();
-               return;
-       }
-
-       while (pending) {
-               int bit = __ffs(pending);
-
-               generic_handle_irq(irq_linear_revmap(domain, bit));
-               pending &= ~BIT(bit);
-       }
-}
-
-static void ar71xx_misc_irq_unmask(struct irq_data *d)
-{
-       void __iomem *base = irq_data_get_irq_chip_data(d);
-       unsigned int irq = d->hwirq;
-       u32 t;
-
-       t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
-       __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
-
-       /* flush write */
-       __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
-}
-
-static void ar71xx_misc_irq_mask(struct irq_data *d)
-{
-       void __iomem *base = irq_data_get_irq_chip_data(d);
-       unsigned int irq = d->hwirq;
-       u32 t;
-
-       t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
-       __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
-
-       /* flush write */
-       __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
-}
-
-static void ar724x_misc_irq_ack(struct irq_data *d)
-{
-       void __iomem *base = irq_data_get_irq_chip_data(d);
-       unsigned int irq = d->hwirq;
-       u32 t;
-
-       t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
-       __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
-
-       /* flush write */
-       __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
-}
-
-static struct irq_chip ath79_misc_irq_chip = {
-       .name           = "MISC",
-       .irq_unmask     = ar71xx_misc_irq_unmask,
-       .irq_mask       = ar71xx_misc_irq_mask,
-};
-
-static void __init ath79_misc_irq_init(void)
-{
-       if (soc_is_ar71xx() || soc_is_ar913x())
-               ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
-       else if (soc_is_ar724x() ||
-                soc_is_ar933x() ||
-                soc_is_ar934x() ||
-                soc_is_qca955x())
-               ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
-       else
-               BUG();
-
-       ath79_misc_intc_domain_init(NULL, ATH79_CPU_IRQ(6));
-}
 
 static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
 {
@@ -248,69 +164,6 @@ asmlinkage void plat_irq_dispatch(void)
        }
 }
 
-static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
-{
-       irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq);
-       irq_set_chip_data(irq, d->host_data);
-       return 0;
-}
-
-static const struct irq_domain_ops misc_irq_domain_ops = {
-       .xlate = irq_domain_xlate_onecell,
-       .map = misc_map,
-};
-
-static void __init ath79_misc_intc_domain_init(
-       struct device_node *node, int irq)
-{
-       void __iomem *base = ath79_reset_base;
-       struct irq_domain *domain;
-
-       domain = irq_domain_add_legacy(node, ATH79_MISC_IRQ_COUNT,
-                       ATH79_MISC_IRQ_BASE, 0, &misc_irq_domain_ops, base);
-       if (!domain)
-               panic("Failed to add MISC irqdomain");
-
-       /* Disable and clear all interrupts */
-       __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
-       __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
-
-       irq_set_chained_handler_and_data(irq, ath79_misc_irq_handler, domain);
-}
-
-static int __init ath79_misc_intc_of_init(
-       struct device_node *node, struct device_node *parent)
-{
-       int irq;
-
-       irq = irq_of_parse_and_map(node, 0);
-       if (!irq)
-               panic("Failed to get MISC IRQ");
-
-       ath79_misc_intc_domain_init(node, irq);
-       return 0;
-}
-
-static int __init ar7100_misc_intc_of_init(
-       struct device_node *node, struct device_node *parent)
-{
-       ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
-       return ath79_misc_intc_of_init(node, parent);
-}
-
-IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
-               ar7100_misc_intc_of_init);
-
-static int __init ar7240_misc_intc_of_init(
-       struct device_node *node, struct device_node *parent)
-{
-       ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
-       return ath79_misc_intc_of_init(node, parent);
-}
-
-IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
-               ar7240_misc_intc_of_init);
-
 static int __init ar79_cpu_intc_of_init(
        struct device_node *node, struct device_node *parent)
 {
@@ -348,6 +201,8 @@ IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",
 
 void __init arch_init_irq(void)
 {
+       bool misc_is_ar71xx;
+
        if (mips_machtype == ATH79_MACH_GENERIC_OF) {
                irqchip_init();
                return;
@@ -362,7 +217,19 @@ void __init arch_init_irq(void)
        }
 
        mips_cpu_irq_init();
-       ath79_misc_irq_init();
+
+       if (soc_is_ar71xx() || soc_is_ar913x())
+               misc_is_ar71xx = true;
+       else if (soc_is_ar724x() ||
+                soc_is_ar933x() ||
+                soc_is_ar934x() ||
+                soc_is_qca955x())
+               misc_is_ar71xx = false;
+       else
+               BUG();
+       ath79_misc_irq_init(
+               ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,
+               ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);
 
        if (soc_is_ar934x())
                ar934x_ip2_irq_init();

diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
index 2b3487213d1e932247077d8b3f67ba28612f2683..22a2f56ad5e9b4bd8a6a982821ab9590675a5369 100644 (file)
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -144,4 +144,7 @@ static inline u32 ath79_reset_rr(unsigned reg)
 void ath79_device_reset_set(u32 mask);
 void ath79_device_reset_clear(u32 mask);
 
+void ath79_misc_irq_init(void __iomem *regs, int irq,
+                       int irq_base, bool is_ar71xx);
+
 #endif /* __ASM_MACH_ATH79_H */

diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 18caacb60d581e953407ac6cae347c97bf7c4ce7..b873d4a081b404237a675093f7250c3af920ea96 100644 (file)
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -1,5 +1,6 @@
 obj-$(CONFIG_IRQCHIP)                  += irqchip.o
 
+obj-$(CONFIG_ATH79)                    += irq-ath79-misc.o
 obj-$(CONFIG_ARCH_BCM2835)             += irq-bcm2835.o
 obj-$(CONFIG_ARCH_BCM2835)             += irq-bcm2836.o
 obj-$(CONFIG_ARCH_EXYNOS)              += exynos-combiner.o

diff --git a/drivers/irqchip/irq-ath79-misc.c b/drivers/irqchip/irq-ath79-misc.c
new file mode 100644 (file)
index 0000000..aa72907
--- /dev/null
+++ b/drivers/irqchip/irq-ath79-misc.c
@@ -0,0 +1,189 @@
+/*
+ *  Atheros AR71xx/AR724x/AR913x MISC interrupt controller
+ *
+ *  Copyright (C) 2015 Alban Bedel <albeu@free.fr>
+ *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#define AR71XX_RESET_REG_MISC_INT_STATUS       0
+#define AR71XX_RESET_REG_MISC_INT_ENABLE       4
+
+#define ATH79_MISC_IRQ_COUNT                   32
+
+static void ath79_misc_irq_handler(struct irq_desc *desc)
+{
+       struct irq_domain *domain = irq_desc_get_handler_data(desc);
+       struct irq_chip *chip = irq_desc_get_chip(desc);
+       void __iomem *base = domain->host_data;
+       u32 pending;
+
+       chained_irq_enter(chip, desc);
+
+       pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
+                 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+
+       if (!pending) {
+               spurious_interrupt();
+               chained_irq_exit(chip, desc);
+               return;
+       }
+
+       while (pending) {
+               int bit = __ffs(pending);
+
+               generic_handle_irq(irq_linear_revmap(domain, bit));
+               pending &= ~BIT(bit);
+       }
+
+       chained_irq_exit(chip, desc);
+}
+
+static void ar71xx_misc_irq_unmask(struct irq_data *d)
+{
+       void __iomem *base = irq_data_get_irq_chip_data(d);
+       unsigned int irq = d->hwirq;
+       u32 t;
+
+       t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+       __raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+
+       /* flush write */
+       __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+}
+
+static void ar71xx_misc_irq_mask(struct irq_data *d)
+{
+       void __iomem *base = irq_data_get_irq_chip_data(d);
+       unsigned int irq = d->hwirq;
+       u32 t;
+
+       t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+       __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+
+       /* flush write */
+       __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+}
+
+static void ar724x_misc_irq_ack(struct irq_data *d)
+{
+       void __iomem *base = irq_data_get_irq_chip_data(d);
+       unsigned int irq = d->hwirq;
+       u32 t;
+
+       t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
+       __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
+
+       /* flush write */
+       __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
+}
+
+static struct irq_chip ath79_misc_irq_chip = {
+       .name           = "MISC",
+       .irq_unmask     = ar71xx_misc_irq_unmask,
+       .irq_mask       = ar71xx_misc_irq_mask,
+};
+
+static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+{
+       irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq);
+       irq_set_chip_data(irq, d->host_data);
+       return 0;
+}
+
+static const struct irq_domain_ops misc_irq_domain_ops = {
+       .xlate = irq_domain_xlate_onecell,
+       .map = misc_map,
+};
+
+static void __init ath79_misc_intc_domain_init(
+       struct irq_domain *domain, int irq)
+{
+       void __iomem *base = domain->host_data;
+
+       /* Disable and clear all interrupts */
+       __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
+       __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
+
+       irq_set_chained_handler_and_data(irq, ath79_misc_irq_handler, domain);
+}
+
+static int __init ath79_misc_intc_of_init(
+       struct device_node *node, struct device_node *parent)
+{
+       struct irq_domain *domain;
+       void __iomem *base;
+       int irq;
+
+       irq = irq_of_parse_and_map(node, 0);
+       if (!irq) {
+               pr_err("Failed to get MISC IRQ\n");
+               return -EINVAL;
+       }
+
+       base = of_iomap(node, 0);
+       if (!base) {
+               pr_err("Failed to get MISC IRQ registers\n");
+               return -ENOMEM;
+       }
+
+       domain = irq_domain_add_linear(node, ATH79_MISC_IRQ_COUNT,
+                               &misc_irq_domain_ops, base);
+       if (!domain) {
+               pr_err("Failed to add MISC irqdomain\n");
+               return -EINVAL;
+       }
+
+       ath79_misc_intc_domain_init(domain, irq);
+       return 0;
+}
+
+static int __init ar7100_misc_intc_of_init(
+       struct device_node *node, struct device_node *parent)
+{
+       ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
+       return ath79_misc_intc_of_init(node, parent);
+}
+
+IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
+               ar7100_misc_intc_of_init);
+
+static int __init ar7240_misc_intc_of_init(
+       struct device_node *node, struct device_node *parent)
+{
+       ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
+       return ath79_misc_intc_of_init(node, parent);
+}
+
+IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
+               ar7240_misc_intc_of_init);
+
+void __init ath79_misc_irq_init(void __iomem *regs, int irq,
+                               int irq_base, bool is_ar71xx)
+{
+       struct irq_domain *domain;
+
+       if (is_ar71xx)
+               ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
+       else
+               ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
+
+       domain = irq_domain_add_legacy(NULL, ATH79_MISC_IRQ_COUNT,
+                       irq_base, 0, &misc_irq_domain_ops, regs);
+       if (!domain)
+               panic("Failed to create MISC irqdomain");
+
+       ath79_misc_intc_domain_init(domain, irq);
+}