Store SDMA channel and buffer descriptors in IRAM for MX6SL.
This will improve the audio playback power when both the
SDMA and audio buffers are all in IRAM. The DDR will be
self-refresh for longer periods of time.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
+
#
# Automatically generated make config: don't edit
# Linux/arm 3.0.35 Kernel Configuration
# CONFIG_MACH_MX6Q_SABRELITE is not set
CONFIG_MACH_MX6Q_SABRESD=y
# CONFIG_MACH_MX6Q_SABREAUTO is not set
+CONFIG_SDMA_IRAM=y
#
# MX6 Options:
Enabling this will direct all the ENET interrupts to a board specific GPIO.
This will allow the system to enter WAIT mode when ENET is active.
+config SDMA_IRAM
+ bool "Use Internal RAM for SDMA data structures"
+ depends on IMX_SDMA && SOC_IMX6SL
+ help
+ SDMA buffer or control structures are stored in the IRAM/OCRAM
+
+
endif
.secondary = &tzasc2_clk,
},
};
+
#if defined(CONFIG_SDMA_IRAM) || defined(CONFIG_SND_MXC_SOC_IRAM)
static struct clk ocram_clk = {
__INIT_CLK_DEBUG(ocram_clk)
.disable = _clk_disable_inwait,
};
#endif
+
static unsigned long _clk_ipg_perclk_get_rate(struct clk *clk)
{
u32 reg, div;