[PATCH] Small Sequoia cleanup

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index b2b82c75954839bd90c36c02583e4bc0fac8e47b..ddd01c227c78c7a165c080fdf8ae3efe980eb906 100644 (file)
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -359,8 +359,8 @@ int checkboard(void)
        printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 #endif
 
-       rev = *(u8 *)(CFG_CPLD + 0);
-       val = *(u8 *)(CFG_CPLD + 5) & 0x01;
+       rev = *(u8 *)(CFG_BCSR_BASE + 0);
+       val = *(u8 *)(CFG_BCSR_BASE + 5) & 0x01;
        printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 
        if (s != NULL) {

diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 29f3b408d27569e2bddb1827aae34ef8c97cd6d3..8a319250dea794e361649a891b00d7796c5703fd 100644 (file)
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -75,9 +75,7 @@
  * Initial RAM & stack pointer
  *----------------------------------------------------------------------*/
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache    */
-#define CFG_INIT_RAM_OCM       1               /* OCM as init ram      */
 #define CFG_INIT_RAM_ADDR      CFG_OCM_BASE    /* OCM                  */
-
 #define CFG_INIT_RAM_END       (4 << 10)
 #define CFG_GBL_DATA_SIZE      256             /* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
@@ -381,9 +379,6 @@
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
-#define CFG_FLASH              CFG_FLASH_BASE
-#define CFG_NAND               0xD0000000
-#define CFG_CPLD               0xC0000000
 
 /*
  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
@@ -392,25 +387,25 @@
 #define CFG_NAND_CS            3               /* NAND chip connected to CSx   */
 /* Memory Bank 0 (NOR-FLASH) initialization                                    */
 #define CFG_EBC_PB0AP          0x03017200
-#define CFG_EBC_PB0CR          (CFG_FLASH | 0xda000)
+#define CFG_EBC_PB0CR          (CFG_FLASH_BASE | 0xda000)
 
 /* Memory Bank 3 (NAND-FLASH) initialization                                   */
 #define CFG_EBC_PB3AP          0x018003c0
-#define CFG_EBC_PB3CR          (CFG_NAND | 0x1c000)
+#define CFG_EBC_PB3CR          (CFG_NAND_ADDR | 0x1c000)
 #else
 #define CFG_NAND_CS            0               /* NAND chip connected to CSx   */
 /* Memory Bank 3 (NOR-FLASH) initialization                                    */
 #define CFG_EBC_PB3AP          0x03017200
-#define CFG_EBC_PB3CR          (CFG_FLASH | 0xda000)
+#define CFG_EBC_PB3CR          (CFG_FLASH_BASE | 0xda000)
 
 /* Memory Bank 0 (NAND-FLASH) initialization                                   */
 #define CFG_EBC_PB0AP          0x018003c0
-#define CFG_EBC_PB0CR          (CFG_NAND | 0x1c000)
+#define CFG_EBC_PB0CR          (CFG_NAND_ADDR | 0x1c000)
 #endif
 
 /* Memory Bank 2 (CPLD) initialization                                         */
 #define CFG_EBC_PB2AP          0x24814580
-#define CFG_EBC_PB2CR          (CFG_CPLD | 0x38000)
+#define CFG_EBC_PB2CR          (CFG_BCSR_BASE | 0x38000)
 
 /*-----------------------------------------------------------------------
  * NAND FLASH