ENGR00317086-2 gpr: Add dcic mux define in gpr head file

Add dcic mux bit define in gpr head file for both imx6q and imx6sx.

Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit c1522187dbd5109bb3a89b47dc7cdb68d746e38f)

diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index 6cdd5b75156d8520581586b8f52c84d90d0c7a1e..6506a637a7fc8a1ee941ebaeb835275e909788c7 100644 (file)
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -268,15 +268,15 @@
 #define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK         (0x3f << 5)
 #define IMX6Q_GPR10_OCRAM_TZ_EN_MASK           BIT(4)
 #define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK         (0x3 << 2)
-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0     (0x0 << 2)
-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1     (0x1 << 2)
-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0     (0x2 << 2)
-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1     (0x3 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1     (0x0 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS0                (0x1 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS1                (0x2 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_MIPI         (0x3 << 2)
 #define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK         (0x3 << 0)
 #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0     (0x0 << 0)
-#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1     (0x1 << 0)
-#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0     (0x2 << 0)
-#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1     (0x3 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS0                (0x1 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS1                (0x2 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_HDMI         (0x3 << 0)
 
 #define IMX6Q_GPR12_ARMP_IPG_CLK_EN            BIT(27)
 #define IMX6Q_GPR12_ARMP_AHB_CLK_EN            BIT(26)
@@ -420,4 +420,11 @@
 #define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD                  (0x1 << 4)
 #define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI  (0x2 << 4)
 #define IMX6SX_GPR5_CSI1_MUX_CTRL_GND                  (0x3 << 4)
+
+#define IMX6SX_GPR5_DISP_MUX_DCIC2_LCDIF2              (0x0 << 2)
+#define IMX6SX_GPR5_DISP_MUX_DCIC2_LVDS                        (0x1 << 2)
+#define IMX6SX_GPR5_DISP_MUX_DCIC2_MASK                        (0x1 << 2)
+#define IMX6SX_GPR5_DISP_MUX_DCIC1_LCDIF1              (0x0 << 1)
+#define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS                        (0x1 << 1)
+#define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK                        (0x1 << 1)
 #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */