openrisc: entry: Whitespace and comment cleanups

Cleanups to whitespace and add some comments. Reading through the delay
slot logic I noticed some things:
 - Delay slot instructions were not indented
 - Some comments are not lined up
 - Use tabs and spaces consistent with other code

No functional change

Signed-off-by: Stafford Horne <shorne@gmail.com>

diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S
index ba1a361c9a1ef9723eebb8a29c9108807f66f5bb..daae2a423c3ab09e224a3fdfcc2ac56ecea1cffb 100644 (file)
--- a/arch/openrisc/kernel/entry.S
+++ b/arch/openrisc/kernel/entry.S
@@ -228,7 +228,7 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
         * DTLB miss handler in the CONFIG_GUARD_PROTECTED_CORE part
         */
 #ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
-       l.lwz   r6,PT_PC(r3)                  // address of an offending insn
+       l.lwz   r6,PT_PC(r3)               // address of an offending insn
        l.lwz   r6,0(r6)                   // instruction that caused pf
 
        l.srli  r6,r6,26                   // check opcode for jump insn
@@ -244,49 +244,47 @@ EXCEPTION_ENTRY(_data_page_fault_handler)
        l.bf    8f
        l.sfeqi r6,0x12                    // l.jalr
        l.bf    8f
-
-       l.nop
+        l.nop
 
        l.j     9f
-       l.nop
-8:
+        l.nop
 
-       l.lwz   r6,PT_PC(r3)                  // address of an offending insn
+8: // offending insn is in delay slot
+       l.lwz   r6,PT_PC(r3)               // address of an offending insn
        l.addi  r6,r6,4
        l.lwz   r6,0(r6)                   // instruction that caused pf
        l.srli  r6,r6,26                   // get opcode
-9:
+9: // offending instruction opcode loaded in r6
 
 #else
 
-       l.mfspr r6,r0,SPR_SR               // SR
-//     l.lwz   r6,PT_SR(r3)               // ESR
-       l.andi  r6,r6,SPR_SR_DSX           // check for delay slot exception
-       l.sfeqi r6,0x1                     // exception happened in delay slot
-       l.bnf   7f
-       l.lwz   r6,PT_PC(r3)               // address of an offending insn
+       l.mfspr r6,r0,SPR_SR               // SR
+       l.andi  r6,r6,SPR_SR_DSX           // check for delay slot exception
+       l.sfeqi r6,0x1                     // exception happened in delay slot
+       l.bnf   7f
+        l.lwz  r6,PT_PC(r3)               // address of an offending insn
 
-       l.addi  r6,r6,4                    // offending insn is in delay slot
+       l.addi  r6,r6,4                    // offending insn is in delay slot
 7:
        l.lwz   r6,0(r6)                   // instruction that caused pf
        l.srli  r6,r6,26                   // check opcode for write access
 #endif
 
-       l.sfgeui r6,0x33                   // check opcode for write access
+       l.sfgeui r6,0x33                   // check opcode for write access
        l.bnf   1f
        l.sfleui r6,0x37
        l.bnf   1f
        l.ori   r6,r0,0x1                  // write access
        l.j     2f
-       l.nop
+        l.nop
 1:     l.ori   r6,r0,0x0                  // !write access
 2:
 
        /* call fault.c handler in or32/mm/fault.c */
        l.jal   do_page_fault
-       l.nop
+        l.nop
        l.j     _ret_from_exception
-       l.nop
+        l.nop
 
 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
 EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)
@@ -306,9 +304,9 @@ EXCEPTION_ENTRY(_insn_page_fault_handler)
 
        /* call fault.c handler in or32/mm/fault.c */
        l.jal   do_page_fault
-       l.nop
+        l.nop
        l.j     _ret_from_exception
-       l.nop
+        l.nop
 
 
 /* ---[ 0x500: Timer exception ]----------------------------------------- */