]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
arm64: dts: uniphier: switch over to PSCI enable method
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Sun, 16 Oct 2016 14:59:16 +0000 (23:59 +0900)
committerMasahiro Yamada <yamada.masahiro@socionext.com>
Sat, 5 Nov 2016 04:24:57 +0000 (13:24 +0900)
At the first system bring-up, I chose to use spin-table because ARM
Trusted Firmware was not ready for this platform at that moment.

Actually, these SoCs are equipped with EL3 and able to provide PSCI.
Now I finished porting the ATF BL31 for the UniPhier platform, so it
is ready to migrate to PSCI enable method.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi

index 3eb4c42ce7b9500abb19c957985b1ce1be94e927..17bc4b3599123fcf9a8da65248888d209cfd4fb1 100644 (file)
@@ -43,7 +43,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/memreserve/ 0x80000000 0x00000008;    /* cpu-release-addr */
+/memreserve/ 0x80000000 0x00080000;
 
 / {
        compatible = "socionext,uniphier-ld11";
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0 0x000>;
-                       enable-method = "spin-table";
-                       cpu-release-addr = <0 0x80000000>;
+                       enable-method = "psci";
                };
 
                cpu1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0 0x001>;
-                       enable-method = "spin-table";
-                       cpu-release-addr = <0 0x80000000>;
+                       enable-method = "psci";
                };
        };
 
+       psci {
+               compatible = "arm,psci-1.0";
+               method = "smc";
+       };
+
        clocks {
                refclk: ref {
                        compatible = "fixed-clock";
index 56a1b2e92cf32e804c9a71abbf8308e8c8168526..c8ebe7e5280984dfcdfd4909fe5f8b0c21db854d 100644 (file)
@@ -43,7 +43,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/memreserve/ 0x80000000 0x00000008;    /* cpu-release-addr */
+/memreserve/ 0x80000000 0x00080000;
 
 / {
        compatible = "socionext,uniphier-ld20";
                        device_type = "cpu";
                        compatible = "arm,cortex-a72", "arm,armv8";
                        reg = <0 0x000>;
-                       enable-method = "spin-table";
-                       cpu-release-addr = <0 0x80000000>;
+                       enable-method = "psci";
                };
 
                cpu1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a72", "arm,armv8";
                        reg = <0 0x001>;
-                       enable-method = "spin-table";
-                       cpu-release-addr = <0 0x80000000>;
+                       enable-method = "psci";
                };
 
                cpu2: cpu@100 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0 0x100>;
-                       enable-method = "spin-table";
-                       cpu-release-addr = <0 0x80000000>;
+                       enable-method = "psci";
                };
 
                cpu3: cpu@101 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0 0x101>;
-                       enable-method = "spin-table";
-                       cpu-release-addr = <0 0x80000000>;
+                       enable-method = "psci";
                };
        };
 
+       psci {
+               compatible = "arm,psci-1.0";
+               method = "smc";
+       };
+
        clocks {
                refclk: ref {
                        compatible = "fixed-clock";