]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
ALSA: firewire-digi00x: add support of asynchronous transaction for incoming MIDI...
authorTakashi Sakamoto <o-takashi@sakamocchi.jp>
Sun, 11 Oct 2015 03:30:17 +0000 (12:30 +0900)
committerTakashi Iwai <tiwai@suse.de>
Sun, 11 Oct 2015 16:26:09 +0000 (18:26 +0200)
Digi 00x series has two types of model; rack and console. The console
models have physical controls. The model can transmit control messages.
These control messages are transferred by asynchronous transactions to
registered address.

This commit supports the asynchronous transaction.

Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
sound/firewire/digi00x/digi00x-transaction.c
sound/firewire/digi00x/digi00x.h

index 49372901a1e118d01e02ffc67ed3313211573472..8bf5ed5e5f3ef1626543b6ddcf5959f845662ca0 100644 (file)
@@ -9,6 +9,28 @@
 #include <sound/asound.h>
 #include "digi00x.h"
 
+static void handle_midi_control(struct snd_dg00x *dg00x, __be32 *buf,
+                               unsigned int length)
+{
+       struct snd_rawmidi_substream *substream;
+       unsigned int i;
+       unsigned int len;
+       u8 *b;
+
+       substream = ACCESS_ONCE(dg00x->in_control);
+       if (substream == NULL)
+               return;
+
+       length /= 4;
+
+       for (i = 0; i < length; i++) {
+               b = (u8 *)&buf[i];
+               len = b[3] & 0xf;
+               if (len > 0)
+                       snd_rawmidi_receive(dg00x->in_control, b + 1, len);
+       }
+}
+
 static void handle_unknown_message(struct snd_dg00x *dg00x,
                                   unsigned long long offset, __be32 *buf)
 {
@@ -31,6 +53,8 @@ static void handle_message(struct fw_card *card, struct fw_request *request,
 
        if (offset == dg00x->async_handler.offset)
                handle_unknown_message(dg00x, offset, buf);
+       else if (offset == dg00x->async_handler.offset + 4)
+               handle_midi_control(dg00x, buf, length);
 
        fw_send_response(card, request, RCODE_COMPLETE);
 }
@@ -39,14 +63,25 @@ int snd_dg00x_transaction_reregister(struct snd_dg00x *dg00x)
 {
        struct fw_device *device = fw_parent_device(dg00x->unit);
        __be32 data[2];
+       int err;
 
        /* Unknown. 4bytes. */
        data[0] = cpu_to_be32((device->card->node_id << 16) |
                              (dg00x->async_handler.offset >> 32));
        data[1] = cpu_to_be32(dg00x->async_handler.offset);
+       err = snd_fw_transaction(dg00x->unit, TCODE_WRITE_BLOCK_REQUEST,
+                                DG00X_ADDR_BASE + DG00X_OFFSET_MESSAGE_ADDR,
+                                &data, sizeof(data), 0);
+       if (err < 0)
+               return err;
+
+       /* Asynchronous transactions for MIDI control message. */
+       data[0] = cpu_to_be32((device->card->node_id << 16) |
+                             (dg00x->async_handler.offset >> 32));
+       data[1] = cpu_to_be32(dg00x->async_handler.offset + 4);
        return snd_fw_transaction(dg00x->unit, TCODE_WRITE_BLOCK_REQUEST,
-                                  DG00X_ADDR_BASE + DG00X_OFFSET_MESSAGE_ADDR,
-                                  &data, sizeof(data), 0);
+                                 DG00X_ADDR_BASE + DG00X_OFFSET_MIDI_CTL_ADDR,
+                                 &data, sizeof(data), 0);
 }
 
 int snd_dg00x_transaction_register(struct snd_dg00x *dg00x)
@@ -57,7 +92,7 @@ int snd_dg00x_transaction_register(struct snd_dg00x *dg00x)
        };
        int err;
 
-       dg00x->async_handler.length = 4;
+       dg00x->async_handler.length = 12;
        dg00x->async_handler.address_callback = handle_message;
        dg00x->async_handler.callback_data = dg00x;
 
index 89494d037da377a6055f129f3916fad424d5e2f7..630f6aabb909a4f8b65d997d01222ade3df03806 100644 (file)
@@ -53,6 +53,9 @@ struct snd_dg00x {
        /* For asynchronous messages. */
        struct fw_address_handler async_handler;
        u32 msg;
+
+       /* For asynchronous MIDI controls. */
+       struct snd_rawmidi_substream *in_control;
 };
 
 #define DG00X_ADDR_BASE                0xffffe0000000ull