]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
cxgb4vf: Adds SRIOV driver changes for T6 adapter
authorHariprasad Shenai <hariprasad@chelsio.com>
Tue, 2 Jun 2015 08:29:40 +0000 (13:59 +0530)
committerDavid S. Miller <davem@davemloft.net>
Tue, 2 Jun 2015 05:14:35 +0000 (22:14 -0700)
Adds vnic driver register related changes for T6 adapter

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/chelsio/cxgb4vf/sge.c
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_common.h
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c

index be4ab09d11d74a6eaf29c690ad7686af9399f45c..ad53e5ad2acd05afa1b94c09f7e2c1be8f4599a6 100644 (file)
@@ -524,7 +524,7 @@ static void unmap_rx_buf(struct adapter *adapter, struct sge_fl *fl)
  */
 static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
 {
-       u32 val;
+       u32 val = adapter->params.arch.sge_fl_db;
 
        /* The SGE keeps track of its Producer and Consumer Indices in terms
         * of Egress Queue Units so we can only tell it about integral numbers
@@ -532,11 +532,9 @@ static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
         */
        if (fl->pend_cred >= FL_PER_EQ_UNIT) {
                if (is_t4(adapter->params.chip))
-                       val = PIDX_V(fl->pend_cred / FL_PER_EQ_UNIT);
+                       val |= PIDX_V(fl->pend_cred / FL_PER_EQ_UNIT);
                else
-                       val = PIDX_T5_V(fl->pend_cred / FL_PER_EQ_UNIT) |
-                             DBTYPE_F;
-               val |= DBPRIO_F;
+                       val |= PIDX_T5_V(fl->pend_cred / FL_PER_EQ_UNIT);
 
                /* Make sure all memory writes to the Free List queue are
                 * committed before we tell the hardware about them.
@@ -1084,7 +1082,7 @@ static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *tq,
  * Figure out what HW csum a packet wants and return the appropriate control
  * bits.
  */
-static u64 hwcsum(const struct sk_buff *skb)
+static u64 hwcsum(enum chip_type chip, const struct sk_buff *skb)
 {
        int csum_type;
        const struct iphdr *iph = ip_hdr(skb);
@@ -1116,11 +1114,16 @@ nocsum:
                        goto nocsum;
        }
 
-       if (likely(csum_type >= TX_CSUM_TCPIP))
-               return TXPKT_CSUM_TYPE_V(csum_type) |
-                       TXPKT_IPHDR_LEN_V(skb_network_header_len(skb)) |
-                       TXPKT_ETHHDR_LEN_V(skb_network_offset(skb) - ETH_HLEN);
-       else {
+       if (likely(csum_type >= TX_CSUM_TCPIP)) {
+               u64 hdr_len = TXPKT_IPHDR_LEN_V(skb_network_header_len(skb));
+               int eth_hdr_len = skb_network_offset(skb) - ETH_HLEN;
+
+               if (chip <= CHELSIO_T5)
+                       hdr_len |= TXPKT_ETHHDR_LEN_V(eth_hdr_len);
+               else
+                       hdr_len |= T6_TXPKT_ETHHDR_LEN_V(eth_hdr_len);
+               return TXPKT_CSUM_TYPE_V(csum_type) | hdr_len;
+       } else {
                int start = skb_transport_offset(skb);
 
                return TXPKT_CSUM_TYPE_V(csum_type) |
@@ -1308,10 +1311,15 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
                 * accounting.
                 */
                cpl = (void *)(lso + 1);
-               cntrl = (TXPKT_CSUM_TYPE_V(v6 ?
+
+               if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
+                       cntrl = TXPKT_ETHHDR_LEN_V(eth_xtra_len);
+               else
+                       cntrl = T6_TXPKT_ETHHDR_LEN_V(eth_xtra_len);
+
+               cntrl |= TXPKT_CSUM_TYPE_V(v6 ?
                                           TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
-                        TXPKT_IPHDR_LEN_V(l3hdr_len) |
-                        TXPKT_ETHHDR_LEN_V(eth_xtra_len));
+                        TXPKT_IPHDR_LEN_V(l3hdr_len);
                txq->tso++;
                txq->tx_cso += ssi->gso_segs;
        } else {
@@ -1328,7 +1336,8 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
                 */
                cpl = (void *)(wr + 1);
                if (skb->ip_summed == CHECKSUM_PARTIAL) {
-                       cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS_F;
+                       cntrl = hwcsum(adapter->params.chip, skb) |
+                               TXPKT_IPCSUM_DIS_F;
                        txq->tx_cso++;
                } else
                        cntrl = TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F;
@@ -2247,6 +2256,8 @@ int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
        cmd.iqaddr = cpu_to_be64(rspq->phys_addr);
 
        if (fl) {
+               enum chip_type chip =
+                       CHELSIO_CHIP_VERSION(adapter->params.chip);
                /*
                 * Allocate the ring for the hardware free list (with space
                 * for its status page) along with the associated software
@@ -2286,7 +2297,9 @@ int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
                cmd.fl0dcaen_to_fl0cidxfthresh =
                        cpu_to_be16(
                                FW_IQ_CMD_FL0FBMIN_V(SGE_FETCHBURSTMIN_64B) |
-                               FW_IQ_CMD_FL0FBMAX_V(SGE_FETCHBURSTMAX_512B));
+                               FW_IQ_CMD_FL0FBMAX_V((chip <= CHELSIO_T5) ?
+                                                    FETCHBURSTMAX_512B_X :
+                                                    FETCHBURSTMAX_256B_X));
                cmd.fl0size = cpu_to_be16(flsz);
                cmd.fl0addr = cpu_to_be64(fl->addr);
        }
index 75df25970d5e11cfb2ed88366ecdfdd4e4f044a5..88b8981b47517ecf302667751ee86e8495d118ba 100644 (file)
@@ -51,6 +51,7 @@
  */
 #define CHELSIO_T4             0x4
 #define CHELSIO_T5             0x5
+#define CHELSIO_T6             0x6
 
 enum chip_type {
        T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
@@ -156,6 +157,12 @@ struct vpd_params {
        u32 cclk;                       /* Core Clock (KHz) */
 };
 
+/* Stores chip specific parameters */
+struct arch_specific_params {
+       u32 sge_fl_db;
+       u16 mps_tcam_size;
+};
+
 /*
  * Global Receive Side Scaling (RSS) parameters in host-native format.
  */
@@ -215,6 +222,7 @@ struct adapter_params {
        struct vpd_params vpd;          /* Vital Product Data */
        struct rss_params rss;          /* Receive Side Scaling */
        struct vf_resources vfres;      /* Virtual Function Resource limits */
+       struct arch_specific_params arch; /* chip specific params */
        enum chip_type chip;            /* chip code */
        u8 nports;                      /* # of Ethernet "ports" */
 };
index 135909ecbc0f54d24968de61f4205890cb728038..0db6dc9e9ed25f41273f9767ab470033be40ec5e 100644 (file)
@@ -1191,9 +1191,7 @@ int t4vf_alloc_mac_filt(struct adapter *adapter, unsigned int viid, bool free,
        unsigned nfilters = 0;
        unsigned int rem = naddr;
        struct fw_vi_mac_cmd cmd, rpl;
-       unsigned int max_naddr = is_t4(adapter->params.chip) ?
-                                NUM_MPS_CLS_SRAM_L_INSTANCES :
-                                NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
+       unsigned int max_naddr = adapter->params.arch.mps_tcam_size;
 
        if (naddr > max_naddr)
                return -EINVAL;
@@ -1285,9 +1283,7 @@ int t4vf_change_mac(struct adapter *adapter, unsigned int viid,
        struct fw_vi_mac_exact *p = &cmd.u.exact[0];
        size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
                                             u.exact[1]), 16);
-       unsigned int max_naddr = is_t4(adapter->params.chip) ?
-                                NUM_MPS_CLS_SRAM_L_INSTANCES :
-                                NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
+       unsigned int max_mac_addr = adapter->params.arch.mps_tcam_size;
 
        /*
         * If this is a new allocation, determine whether it should be
@@ -1310,7 +1306,7 @@ int t4vf_change_mac(struct adapter *adapter, unsigned int viid,
        if (ret == 0) {
                p = &rpl.u.exact[0];
                ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
-               if (ret >= max_naddr)
+               if (ret >= max_mac_addr)
                        ret = -ENOMEM;
        }
        return ret;
@@ -1590,11 +1586,25 @@ int t4vf_prep_adapter(struct adapter *adapter)
        switch (CHELSIO_PCI_ID_VER(adapter->pdev->device)) {
        case CHELSIO_T4:
                adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, 0);
+               adapter->params.arch.sge_fl_db = DBPRIO_F;
+               adapter->params.arch.mps_tcam_size =
+                               NUM_MPS_CLS_SRAM_L_INSTANCES;
                break;
 
        case CHELSIO_T5:
                chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A));
                adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, chipid);
+               adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
+               adapter->params.arch.mps_tcam_size =
+                               NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
+               break;
+
+       case CHELSIO_T6:
+               chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A));
+               adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, chipid);
+               adapter->params.arch.sge_fl_db = 0;
+               adapter->params.arch.mps_tcam_size =
+                               NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
                break;
        }