IB/mlx5: Fix UMR size calculation

Translation table updates of large UMR may require multiple post send
operations. The last operations can be in various lengths, but current
code set them to be the same length.

Fixes: 7d0cc6edcc70 ('IB/mlx5: Add MR cache for large UMR regions')
Signed-off-by: Artemy Kovalyov <artemyko@mellanox.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Signed-off-by: Doug Ledford <dledford@redhat.com>

diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c
index 1f09e11fa694d03ae35205ad9280020d621ff2fe..9a74260e9899a1c4a1d3d1d0a7817ccf00e5de43 100644 (file)
--- a/drivers/infiniband/hw/mlx5/mr.c
+++ b/drivers/infiniband/hw/mlx5/mr.c
@@ -1045,8 +1045,9 @@ int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
        for (pages_mapped = 0;
             pages_mapped < pages_to_map && !err;
             pages_mapped += pages_iter, idx += pages_iter) {
+               npages = min_t(int, pages_iter, pages_to_map - pages_mapped);
                dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE);
-               npages = populate_xlt(mr, idx, pages_iter, xlt,
+               npages = populate_xlt(mr, idx, npages, xlt,
                                      page_shift, size, flags);
 
                dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE);