source "arch/arm/mach-tegra/Kconfig"
-source "arch/arm/cpu/armv7/uniphier/Kconfig"
+source "arch/arm/mach-uniphier/Kconfig"
source "arch/arm/mach-versatile/Kconfig"
# SPDX-License-Identifier: GPL-2.0+
#
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
-CONFIG_CPU_V7=
-CONFIG_CPU_ARM720T=y
-endif
-
-# This selects which instruction set is used.
-arch-$(CONFIG_CPU_ARM720T) =-march=armv4
-arch-$(CONFIG_CPU_ARM920T) =-march=armv4
-arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te
-arch-$(CONFIG_CPU_ARM946ES) =-march=armv4
-arch-$(CONFIG_CPU_SA1100) =-march=armv4
-arch-$(CONFIG_CPU_PXA) =
-arch-$(CONFIG_CPU_ARM1136) =-march=armv5
-arch-$(CONFIG_CPU_ARM1176) =-march=armv5t
-arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, -march=armv5)
-arch-$(CONFIG_ARM64) =-march=armv8-a
-
-# Evaluate arch cc-option calls now
-arch-y := $(arch-y)
-
-# This selects how we optimise for the processor.
-tune-$(CONFIG_CPU_ARM720T) =-mtune=arm7tdmi
-tune-$(CONFIG_CPU_ARM920T) =
-tune-$(CONFIG_CPU_ARM926EJS) =
-tune-$(CONFIG_CPU_ARM946ES) =
-tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100
-tune-$(CONFIG_CPU_PXA) =-mcpu=xscale
-tune-$(CONFIG_CPU_ARM1136) =
-tune-$(CONFIG_CPU_ARM1176) =
-tune-$(CONFIG_CPU_V7) =
-tune-$(CONFIG_ARM64) =
-
-# Evaluate tune cc-option calls now
-tune-y := $(tune-y)
-
-PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
-
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
machine-$(CONFIG_ARCH_AT91) += at91
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_TEGRA) += tegra
+machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
+machine-$(CONFIG_ARCH_VERSATILE) += versatile
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
obj-y += cache_v7.o
-obj-y += cpu.o cp15.o
+obj-y += cpu.o
obj-y += syslib.o
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_SOC_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)
obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
+obj-$(CONFIG_BCM2835) += bcm2835/
obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
- early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
-obj-$(CONFIG_SPL_DM) += platdevice.o
+obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
+ pll_spectrum.o umc_init.o ddrphy_init.o
else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
endif
obj-y += boot-mode.o
/*
- * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <common.h>
#include <asm/io.h>
-#include <mach/sc-regs.h>
+#include <asm/arch/sc-regs.h>
void clkrst_init(void)
{
/* deassert reset */
tmp = readl(SC_RSTCTRL);
-#ifdef CONFIG_UNIPHIER_ETH
- tmp |= SC_RSTCTRL_NRST_ETHER;
-#endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- tmp |= SC_RSTCTRL_NRST_STDMAC;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_RSTCTRL_NRST_NAND;
-#endif
+ tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
+ | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
/* privide clocks */
tmp = readl(SC_CLKCTRL);
-#ifdef CONFIG_UNIPHIER_ETH
- tmp |= SC_CLKCTRL_CEN_ETHER;
-#endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_CLKCTRL_CEN_NAND;
-#endif
+ tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
+ | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}
/*
- * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <asm/io.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+#include <asm/arch/sbc-regs.h>
+#include <asm/arch/sg-regs.h>
void sbc_init(void)
{
tmp &= 0xfffffcff;
writel(tmp, PC0CTRL);
- /*
- * Only CS1 is connected to support card.
- * BKSZ[1:0] should be set to "01".
- */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
+ /* XECS1: sub/boot memory (boot swap = off/on) */
+ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+ writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+ writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+ writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
- if (boot_is_swapped()) {
- /*
- * Boot Swap On: boot from external NOR/SRAM
- * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
- *
- * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
- * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
- */
- writel(0x0000bc01, SBBASE0);
- } else {
- /*
- * Boot Swap Off: boot from mask ROM
- * 0x00000000-0x01ffffff: mask ROM
- * 0x02000000-0x03efffff: memory bank (31MB)
- * 0x03f00000-0x03ffffff: peripherals (1MB)
- */
- writel(0x0000be01, SBBASE0); /* dummy */
- writel(0x0200be01, SBBASE1);
- }
+#if !defined(CONFIG_SPL_BUILD)
+ /* XECS0: boot/sub memory (boot swap = off/on) */
+ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
+ writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
+ writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
+ writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
+#endif
+ /* XECS3: peripherals */
+ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
+ writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
+ writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
+ writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
+
+ /* base address regsiters */
+ writel(0x0000bc01, SBBASE0);
+ writel(0x0400bc01, SBBASE1);
+ writel(0x0800bf01, SBBASE3);
+
+#if !defined(CONFIG_SPL_BUILD)
+ /* enable access to sub memory when boot swap is on */
+ sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
+#endif
+ sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
}
/*
- * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <common.h>
#include <asm/io.h>
-#include <mach/sg-regs.h>
+#include <asm/arch/sg-regs.h>
void sg_init(void)
{
u32 tmp;
+ /* Set DDR size */
+ tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
+ tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
+#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
+ tmp |= SG_MEMCONF_SPARSEMEM;
+#endif
+ writel(tmp, SG_MEMCONF);
+
/* Input ports must be enabled before deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 0x1;
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += sg_init.o pll_init.o early_clkrst_init.o \
- early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
-obj-$(CONFIG_SPL_DM) += platdevice.o
+obj-y += sbc_init.o sg_init.o pll_init.o clkrst_init.o \
+ pll_spectrum.o umc_init.o ddrphy_init.o
else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
endif
obj-y += boot-mode.o
/*
- * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <common.h>
#include <asm/io.h>
-#include <mach/sc-regs.h>
+#include <asm/arch/sc-regs.h>
void clkrst_init(void)
{
/* deassert reset */
tmp = readl(SC_RSTCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
- SC_RSTCTRL_NRST_GIO;
-#endif
-#ifdef CONFIG_UNIPHIER_ETH
- tmp |= SC_RSTCTRL_NRST_ETHER;
-#endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- tmp |= SC_RSTCTRL_NRST_STDMAC;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_RSTCTRL_NRST_NAND;
-#endif
+ tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
+ | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- tmp = readl(SC_RSTCTRL2);
- tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
- writel(tmp, SC_RSTCTRL2);
- readl(SC_RSTCTRL2); /* dummy read */
-#endif
-
/* privide clocks */
tmp = readl(SC_CLKCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
- SC_CLKCTRL_CEN_GIO;
-#endif
-#ifdef CONFIG_UNIPHIER_ETH
- tmp |= SC_CLKCTRL_CEN_ETHER;
-#endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
-#endif
-#ifdef CONFIG_NAND_DENALI
- tmp |= SC_CLKCTRL_CEN_NAND;
-#endif
+ tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
+ | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}
/*
- * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <asm/io.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
+#include <asm/arch/sbc-regs.h>
+#include <asm/arch/sg-regs.h>
void sbc_init(void)
{
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
/*
* Only CS1 is connected to support card.
* BKSZ[1:0] should be set to "01".
/*
* Boot Swap Off: boot from mask ROM
* 0x00000000-0x01ffffff: mask ROM
- * 0x02000000-0x03efffff: memory bank (31MB)
- * 0x03f00000-0x03ffffff: peripherals (1MB)
+ * 0x02000000-0x3effffff: memory bank (31MB)
+ * 0x03f00000-0x3fffffff: peripherals (1MB)
*/
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
}
+#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+#if !defined(CONFIG_SPL_BUILD)
+ /* XECS0: boot/sub memory (boot swap = off/on) */
+ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
+ writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
+ writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
+ writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
+#endif
+ /* XECS1: sub/boot memory (boot swap = off/on) */
+ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+ writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+ writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+ writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+
+ /* XECS3: peripherals */
+ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
+ writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
+ writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
+ writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
+
+ writel(0x0000bc01, SBBASE0); /* boot memory */
+ writel(0x0400bc01, SBBASE1); /* sub memory */
+ writel(0x0800bf01, SBBASE3); /* peripherals */
+
+#if !defined(CONFIG_SPL_BUILD)
+ sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
+#endif
+ sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
+ writel(0x00000001, SG_LOADPINCTRL);
+
+#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */
}
/*
- * Copyright (C) 2011-2015 Panasonic Corporation
+ * Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <common.h>
#include <asm/io.h>
-#include <mach/sg-regs.h>
+#include <asm/arch/sg-regs.h>
void sg_init(void)
{
u32 tmp;
+ /* Set DDR size */
+ tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
+ tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
+#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
+ tmp |= SG_MEMCONF_SPARSEMEM;
+#endif
+ writel(tmp, SG_MEMCONF);
+
/* Input ports must be enabled before deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 1 << 6;
-include $(src)/../ph1-ld4/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
+obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
+ pll_spectrum.o umc_init.o ddrphy_init.o
+else
+obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
+obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
+endif
+
+obj-y += boot-mode.o
-#include "../ph1-ld4/clkrst_init.c"
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sc-regs.h>
+
+void clkrst_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+ tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
+ | SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+ /* privide clocks */
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
+ | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+}
-#include "../ph1-ld4/sbc_init.c"
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sbc-regs.h>
+#include <asm/arch/sg-regs.h>
+
+void sbc_init(void)
+{
+ u32 tmp;
+
+ /* system bus output enable */
+ tmp = readl(PC0CTRL);
+ tmp &= 0xfffffcff;
+ writel(tmp, PC0CTRL);
+
+#if !defined(CONFIG_SPL_BUILD)
+ /* XECS0 : dummy */
+ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
+ writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
+ writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
+ writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
+#endif
+ /* XECS1 : boot memory (always boot swap = on) */
+ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
+ writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
+ writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
+ writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
+
+ /* XECS4 : sub memory */
+ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
+ writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
+ writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
+ writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
+
+ /* XECS5 : peripherals */
+ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
+ writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
+ writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
+ writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
+
+ /* base address regsiters */
+ writel(0x0000bc01, SBBASE0); /* boot memory */
+ writel(0x0900bfff, SBBASE1); /* dummy */
+ writel(0x0400bc01, SBBASE4); /* sub memory */
+ writel(0x0800bf01, SBBASE5); /* peripherals */
+
+ sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
+ sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
+
+ /* dummy read to assure write process */
+ readl(SG_PINCTRL(33));
+}
--- /dev/null
+/*
+ * Copyright (C) 2013 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/arch/led.h>
+#include <asm/arch/sbc-regs.h>
+
+/* Entry point of U-Boot main program for the secondary CPU */
+LENTRY(secondary_entry)
+ mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
+ bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache disable
+ mcr p15, 0, r0, c1, c0, 0
+ mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
+ dsb
+ led_write(C,0,,)
+ ldr r1, =ROM_BOOT_ROMRSV2
+ mov r0, #0
+ str r0, [r1]
+0: wfe
+ ldr r4, [r1] @ r4: entry point for secondary CPUs
+ cmp r4, #0
+ beq 0b
+ led_write(C, P, U, 1)
+ bx r4 @ secondary CPUs jump to linux
+ENDPROC(secondary_entry)
+
+ENTRY(wakeup_secondary)
+ ldr r1, =ROM_BOOT_ROMRSV2
+0: ldr r0, [r1]
+ cmp r0, #0
+ bne 0b
+
+ /* set entry address and send event to the secondary CPU */
+ ldr r0, =secondary_entry
+ str r0, [r1]
+ ldr r0, [r1] @ make sure store is complete
+ mov r0, #0x100
+0: subs r0, r0, #1 @ I don't know the reason, but without this wait
+ bne 0b @ fails to wake up the secondary CPU
+ sev
+
+ /* wait until the secondary CPU reach to secondary_entry */
+0: ldr r0, [r1]
+ cmp r0, #0
+ bne 0b
+ bx lr
+ENDPROC(wakeup_secondary)
projects / karo-tx-uboot.git / commitdiff